)]}'
{
  "commit": "b6748b74d5e85345c2c3fb53b14f1ff2498d17ba",
  "tree": "82b50057667f7d3018795bb46118bde1b19ff9ab",
  "parents": [
    "0f2fc0742b8d22266f65a954691c1eb947968d53"
  ],
  "author": {
    "name": "Sebastian Wiebking",
    "email": "sebastian.wiebking@idpro-online.de",
    "time": "Thu Oct 28 14:29:41 2021 +0200"
  },
  "committer": {
    "name": "Sebastian Wiebking",
    "email": "sebastian.wiebking@idpro-online.de",
    "time": "Thu Oct 28 14:29:41 2021 +0200"
  },
  "message": "Design is DRC clean, Simulation passes for RTL+GL and local precheck was successfull. Seems to me that we are ready to go... (2)\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "01ab06f6be50078dab3fda19d6f3a1a98d5f48eb",
      "old_mode": 33188,
      "old_path": "def/user_proj_example.def",
      "new_id": "d3c9cb4ad781de9f795705f2535165cf7e570ead",
      "new_mode": 33188,
      "new_path": "def/user_proj_example.def"
    },
    {
      "type": "modify",
      "old_id": "224ab885e6ec031d4536a130a12e2d41641f428d",
      "old_mode": 33188,
      "old_path": "def/user_project_wrapper.def",
      "new_id": "3cec3f8a03b4011993eace67826e0f744fe175d3",
      "new_mode": 33188,
      "new_path": "def/user_project_wrapper.def"
    },
    {
      "type": "modify",
      "old_id": "13ed701932665db5a3abbe06c57ee02be8d2bc75",
      "old_mode": 33188,
      "old_path": "gds/user_proj_example.gds",
      "new_id": "f1060b6122e95a03c3c4fac3f99d40323ffd0eb1",
      "new_mode": 33188,
      "new_path": "gds/user_proj_example.gds"
    },
    {
      "type": "modify",
      "old_id": "37439236a23e17e00b9da917b9776771a5d4ab1e",
      "old_mode": 33188,
      "old_path": "gds/user_project_wrapper.gds",
      "new_id": "ad0076426f53f3065889cf7365127240e497388e",
      "new_mode": 33188,
      "new_path": "gds/user_project_wrapper.gds"
    },
    {
      "type": "modify",
      "old_id": "ccf466bb5f626912255dcfea308079018cf9306b",
      "old_mode": 33188,
      "old_path": "lef/user_proj_example.lef",
      "new_id": "a96ee9697c941667b962ae908b2f089475b04828",
      "new_mode": 33188,
      "new_path": "lef/user_proj_example.lef"
    },
    {
      "type": "modify",
      "old_id": "aef3d78ffddad8e03947792015d626a7b8d260c4",
      "old_mode": 33188,
      "old_path": "mag/user_proj_example.mag",
      "new_id": "cadcb9435c230d8e6ee8bdc92dd2baaf6f8e561f",
      "new_mode": 33188,
      "new_path": "mag/user_proj_example.mag"
    },
    {
      "type": "modify",
      "old_id": "e20a522f301fce0954b43bfffa5f02a86d9a34dc",
      "old_mode": 33188,
      "old_path": "mag/user_project_wrapper.mag",
      "new_id": "fa43d9655ed941e9f92a07f5c3de4ee60747faad",
      "new_mode": 33188,
      "new_path": "mag/user_project_wrapper.mag"
    },
    {
      "type": "modify",
      "old_id": "99a043b92fd83404cbb48576ccd8512c980f734a",
      "old_mode": 33188,
      "old_path": "maglef/user_proj_example.mag",
      "new_id": "a7d65bd99ec3a8f67419eba01814107c3e4dae95",
      "new_mode": 33188,
      "new_path": "maglef/user_proj_example.mag"
    },
    {
      "type": "modify",
      "old_id": "a426f7d689d7cb742c50ed8d796ad04eb034abe1",
      "old_mode": 33188,
      "old_path": "maglef/user_project_wrapper.mag",
      "new_id": "06d74ec0296241066b8fabac63e2988a8521f397",
      "new_mode": 33188,
      "new_path": "maglef/user_project_wrapper.mag"
    },
    {
      "type": "modify",
      "old_id": "c33c170991b3487c0530be579595c69d943a1261",
      "old_mode": 33261,
      "old_path": "openlane/user_proj_example/config.tcl",
      "new_id": "54b73b950fd54d5a3395f7910f0fecc3bd9a7980",
      "new_mode": 33261,
      "new_path": "openlane/user_proj_example/config.tcl"
    },
    {
      "type": "modify",
      "old_id": "400af7809b9d2887b139c05e9bf296b6598cf292",
      "old_mode": 33188,
      "old_path": "signoff/user_proj_example/final_summary_report.csv",
      "new_id": "b3241f52e5cbce8d1bed51347bc097793d88bf9e",
      "new_mode": 33188,
      "new_path": "signoff/user_proj_example/final_summary_report.csv"
    },
    {
      "type": "modify",
      "old_id": "e241b37c723f5871276a944e810d344f805598f8",
      "old_mode": 33188,
      "old_path": "signoff/user_project_wrapper/final_summary_report.csv",
      "new_id": "f083a2702996ef15fa7a56d90ca284565c71efaa",
      "new_mode": 33188,
      "new_path": "signoff/user_project_wrapper/final_summary_report.csv"
    },
    {
      "type": "modify",
      "old_id": "2f0fcafe29e48622984ce0229b01beab4bc81ad4",
      "old_mode": 33188,
      "old_path": "spi/lvs/user_proj_example.spice",
      "new_id": "3154bd3e9e1cc483831e4ffea5065577fe38efde",
      "new_mode": 33188,
      "new_path": "spi/lvs/user_proj_example.spice"
    },
    {
      "type": "modify",
      "old_id": "d87238f0e5affdad2cdf0f2208e94beef2bb33bc",
      "old_mode": 33188,
      "old_path": "verilog/dv/Makefile",
      "new_id": "a573e2315087f1308f36a2d14e98a6d3d9799167",
      "new_mode": 33188,
      "new_path": "verilog/dv/Makefile"
    },
    {
      "type": "modify",
      "old_id": "1a86e9007674043f3c1af648653f361982f6fa5f",
      "old_mode": 33188,
      "old_path": "verilog/dv/io_ports/io_ports.c",
      "new_id": "32663559e466b322f89e9659f94e6f8e5810ad0a",
      "new_mode": 33188,
      "new_path": "verilog/dv/io_ports/io_ports.c"
    },
    {
      "type": "modify",
      "old_id": "db46208ad9ee8668ae6d9cd59aae0f12227ae1ec",
      "old_mode": 33188,
      "old_path": "verilog/dv/io_ports/io_ports_tb.v",
      "new_id": "fb882dd212252ffd05e2683faa184242dc22a1d4",
      "new_mode": 33188,
      "new_path": "verilog/dv/io_ports/io_ports_tb.v"
    },
    {
      "type": "delete",
      "old_id": "ba979f7a9ff6183fc0e0cbce245fa8ec9190fa78",
      "old_mode": 33188,
      "old_path": "verilog/dv/la_test1/Makefile",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "220bdfe3e258c752feb43b388a87c37771a5ddd5",
      "old_mode": 33188,
      "old_path": "verilog/dv/la_test1/la_test1.c",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "626e390a7212fbc2a4121ecc693f86155208e6a8",
      "old_mode": 33188,
      "old_path": "verilog/dv/la_test1/la_test1_tb.v",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "0435500a3e89bb3d2242890df799c4ed301c04e5",
      "old_mode": 33188,
      "old_path": "verilog/dv/la_test2/Makefile",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "5875432d2683bc04de3fd49f7c5a10cf0b2e6f5e",
      "old_mode": 33188,
      "old_path": "verilog/dv/la_test2/la_test2.c",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "e09905e603055e7d0a9fb905cf94d7ad1b867f66",
      "old_mode": 33188,
      "old_path": "verilog/dv/la_test2/la_test2_tb.v",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "3a73b997f14ebde920620c2e20ff382b986a4c7d",
      "old_mode": 33188,
      "old_path": "verilog/dv/mprj_stimulus/Makefile",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "e4d0a2db6978cc43067e60cc415bf677eba9f84a",
      "old_mode": 33188,
      "old_path": "verilog/dv/mprj_stimulus/mprj_stimulus.c",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "1409015e71ad8b171d10da7129ab3f26b05df0b7",
      "old_mode": 33188,
      "old_path": "verilog/dv/mprj_stimulus/mprj_stimulus_tb.v",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "1c784c6d7c5e2a9fb157d670649e53f2f80a033b",
      "old_mode": 33188,
      "old_path": "verilog/dv/wb_port/Makefile",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "425c115f6064e5352cddf225b7574ca1e006bbf2",
      "old_mode": 33188,
      "old_path": "verilog/dv/wb_port/wb_port.c",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "b32f900e65e9aa32bd56b9ea7f5348b86b14087b",
      "old_mode": 33188,
      "old_path": "verilog/dv/wb_port/wb_port_tb.v",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "modify",
      "old_id": "97aa7e1d72136b3568756ec77f6d883070c6db4d",
      "old_mode": 33188,
      "old_path": "verilog/gl/user_proj_example.v",
      "new_id": "13bfbf7bab21c78ece7c8f8502f83316f4213458",
      "new_mode": 33188,
      "new_path": "verilog/gl/user_proj_example.v"
    }
  ]
}
