)]}'
{
  "commit": "0f2fc0742b8d22266f65a954691c1eb947968d53",
  "tree": "31b694b1532ff40d11af0e2d0a76bd0a3631ec8e",
  "parents": [
    "46c41b81e390f8fdd87e982d71165fb4af47964b"
  ],
  "author": {
    "name": "Sebastian Wiebking",
    "email": "sebastian.wiebking@idpro-online.de",
    "time": "Thu Oct 28 14:26:15 2021 +0200"
  },
  "committer": {
    "name": "Sebastian Wiebking",
    "email": "sebastian.wiebking@idpro-online.de",
    "time": "Thu Oct 28 14:26:15 2021 +0200"
  },
  "message": "Design is DRC clean, Simulation passes for RTL+GL and local precheck was successfull. Seems to me that we are ready to go...\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "c812f78c9a808d813b2008153bf1e61a635beb0c",
      "new_mode": 33188,
      "new_path": "verilog/dv/io_ports/wishboneSlaveCfg.gtkw"
    }
  ]
}