v {xschem version=2.9.9 file_version=1.2 }
G {}
K {}
V {}
S {}
E {}
N -110 80 -110 110 { lab=vref}
N -110 170 -110 210 { lab=GND}
N 820 -420 1190 -420 { lab=feedback_p}
N 690 -240 740 -240 { lab=vin_p}
N 1350 -280 1350 -250 { lab=vdd}
N 1350 -210 1350 -180 { lab=GND}
N 690 140 740 140 { lab=vin_n}
N 1340 120 1340 150 { lab=vdd}
N 1340 190 1340 220 { lab=GND}
N 2230 -230 2310 -230 { lab=audio_p}
N 2250 -230 2250 -220 { lab=audio_p}
N 2250 -160 2250 -140 { lab=GND}
N 2250 240 2250 260 { lab=GND}
N 670 -240 690 -240 { lab=vin_p}
N 1390 170 1400 170 { lab=vcmp_n}
N -20 80 -20 110 { lab=vdd}
N -20 170 -20 200 { lab=GND}
N 1550 -290 1550 -270 { lab=vdd}
N 1550 -190 1550 -170 { lab=GND}
N 1550 110 1550 130 { lab=vdd}
N 1550 210 1550 230 { lab=GND}
N 1400 170 1420 170 { lab=vcmp_n}
N 2220 180 2250 180 { lab=audio_n}
N 2310 -230 2310 -20 { lab=audio_p}
N 2310 -20 2310 -10 { lab=audio_p}
N 2310 50 2310 180 { lab=audio_n}
N 2250 180 2310 180 { lab=audio_n}
N 1010 -90 1220 -90 { lab=vtriang}
N 190 -40 350 -40 { lab=#net1}
N 360 -20 390 -20 { lab=vref}
N 360 -40 390 -40 { lab=#net1}
N 510 -110 510 -90 { lab=vdd}
N 510 -10 510 10 { lab=GND}
N 820 -420 820 -260 { lab=feedback_p}
N 740 -260 740 -240 { lab=vin_p}
N 800 -260 820 -260 { lab=feedback_p}
N 800 140 820 140 { lab=feedback_n}
N 1400 -230 1420 -230 { lab=vcmp_p}
N 1070 -190 1070 -180 { lab=GND}
N 850 -80 880 -80 { lab=vbias2}
N 850 -60 880 -60 { lab=vref}
N 1010 -60 1060 -60 { lab=vsquare}
N 830 390 1210 390 { lab=feedback_n}
N 830 140 830 390 { lab=feedback_n}
N 190 20 190 40 { lab=GND}
N 1250 -420 1850 -420 { lab=out_p}
N 1270 390 1840 390 { lab=out_n}
N 850 -100 880 -100 { lab=vbias1}
N 350 -40 360 -40 { lab=#net1}
N 360 -60 390 -60 { lab=vbias4}
N 360 -80 390 -80 { lab=vbias3}
N 740 -150 740 -120 { lab=#net2}
N 740 -150 940 -150 { lab=#net2}
N 940 -150 940 -130 { lab=#net2}
N 940 -130 940 -120 { lab=#net2}
N 740 -60 740 -40 { lab=GND}
N 670 140 690 140 { lab=vin_n}
N 630 -240 630 -60 { lab=vin_p}
N 630 -240 670 -240 { lab=vin_p}
N 630 -40 630 140 { lab=vin_n}
N 630 140 670 140 { lab=vin_n}
N 2040 -420 2040 -30 { lab=out_p}
N 2040 -10 2040 380 { lab=out_n}
N 2040 380 2040 390 { lab=out_n}
N 1840 390 2040 390 { lab=out_n}
N 1850 -420 2040 -420 { lab=out_p}
N 1680 160 1710 160 { lab=vn_p}
N 1710 -10 1710 160 { lab=vn_p}
N 1710 -10 1740 -10 { lab=vn_p}
N 1670 180 1740 180 { lab=vn_n}
N 1740 10 1740 180 { lab=vn_n}
N 1670 -240 1730 -240 { lab=vp_p}
N 1730 -240 1740 -240 { lab=vp_p}
N 1740 -240 1740 -50 { lab=vp_p}
N 1670 -220 1700 -220 { lab=vp_n}
N 1700 -220 1700 -30 { lab=vp_n}
N 1700 -30 1740 -30 { lab=vp_n}
N 1860 -100 1860 -60 { lab=#net3}
N 1890 -100 1890 -60 { lab=#net3}
N 1800 -200 1800 -150 { lab=GND}
N 1800 -300 1800 -260 { lab=#net3}
N 1800 -300 1860 -300 { lab=#net3}
N 1860 -300 1860 -100 { lab=#net3}
N 1860 -100 1890 -100 { lab=#net3}
N 2040 180 2160 180 { lab=out_n}
N 2040 -230 2170 -230 { lab=out_p}
N 1890 20 1890 70 { lab=GND}
N 1670 160 1680 160 { lab=vn_p}
N 820 140 830 140 { lab=feedback_n}
N 1070 -340 1070 -290 { lab=vdd}
N 1070 -230 1070 -190 { lab=GND}
N 900 -240 920 -240 { lab=vref}
N 820 -280 870 -280 { lab=feedback_p}
N 870 -280 920 -280 { lab=feedback_p}
N 900 -260 920 -260 { lab=vbias5}
N 1220 -260 1240 -260 { lab=error_p}
N 1240 -260 1240 -250 { lab=error_p}
N 1240 -250 1290 -250 { lab=error_p}
N 1220 -230 1290 -230 { lab=vtriang}
N 1220 -230 1220 -90 { lab=vtriang}
N 1240 -210 1290 -210 { lab=vbias7}
N 940 -40 940 0 { lab=GND}
N 1070 90 1070 130 { lab=vdd}
N 1070 190 1070 210 { lab=GND}
N 830 140 920 140 { lab=feedback_n}
N 880 160 920 160 { lab=vbias6}
N 880 180 920 180 { lab=vref}
N 1250 190 1280 190 { lab=vbias8}
N 1220 150 1220 160 { lab=error_n}
N 1220 150 1280 150 { lab=error_n}
N 1220 -90 1220 120 { lab=vtriang}
N 1220 120 1260 120 { lab=vtriang}
N 1260 120 1260 170 { lab=vtriang}
N 1260 170 1280 170 { lab=vtriang}
N 480 280 480 360 { lab=#net4}
N 480 560 480 610 { lab=GND}
N 480 190 480 220 { lab=vdd}
N 580 390 630 390 { lab=vbias1}
N 580 410 630 410 { lab=vbias2}
N 580 430 630 430 { lab=vbias3}
N 580 450 630 450 { lab=vbias4}
N 580 470 630 470 { lab=vbias5}
N 580 490 630 490 { lab=vbias6}
N 580 510 630 510 { lab=vbias7}
N 580 530 630 530 { lab=vbias8}
C {vsource.sym} 190 -10 0 0 {name=V1 value="sin(0.9 0.4 5k)"}
C {code_shown.sym} -860 -420 0 0 {name=s2 only_toplevel=false value="
.option rshunt=1e20
.nodeset V(audio_p)=0.9 V(audio_n)=0.9 V(vp_p)=0.79 V(vn_p)=0 V(vcmp_p)=0.859
+ V(vp_n)=0.79 V(vn_n)=0 V(vcmp_n)=0.859 v(vin_p)=0.9 v(vin_n)=0.9 v(vtriang)=0.9
*.nodeset all=0.9
*.option VNTOL=1e-6 ABSTOL=1e-9
*.option savecurrents
*set the absolute voltage error tolerance and absolute current error tolerance
.control
save out_p out_n audio_p audio_n I(V4) I(V2) @r6[i] @r1[i] i(v3) i(v6) vtriang vin_p vin_n error_p error_n vcmp_p vcmp_n vp_p vp_n vn_p vn_n
*save vtriang audio_p audio_n I(V2) @r6[i] out_p out_n
*op
tran 3n 10m 0.1m
*linearize V(audio)
*linearize V(out)
*fft V(out)
*fft V(audio)
*plot mag(V(audio))
*plot mag(V(out))
let pout=@r6[i]*(V(audio_p)-V(audio_n))
let pin=1.8*(I(V4)+I(V2)+I(V3))
meas tran pload avg pout from=2m to=9m
meas tran p_supply avg pin from=2m to=9m
*print pload/p_supply
set nfreqs=20
*fourier 10k V(out_p)-V(out_n)

fourier 5k V(audio_p)-V(audio_n)
write class_d_5k_04_post_notflat.raw

.endc


"}
C {netlist_not_shown.sym} 370 -350 0 0 {name=TT_MODELS1
spice_ignore=false
only_toplevel=true
format="tcleval( @value )"
value="
.include /home/eda/pdk/skywater-pdk/libraries/sky130_fd_pr_ngspice/latest/models/corners/tt.spice
.include /home/eda/magic/class_d_audio_amplifier/OTA/OTA_int_post.spice
.include /home/eda/magic/class_d_audio_amplifier/OTA/OTA_post.spice
.include /home/eda/magic/class_d_audio_amplifier/S_to_D/S_to_D_post.spice
.include /home/eda/magic/class_d_audio_amplifier/S_to_D/S_to_D_revised_post.spice
.include /home/eda/magic/class_d_audio_amplifier/triang/triangle_post.spice
.include /home/eda/magic/class_d_audio_amplifier/triang/triangle_revised_post.spice
.include /home/eda/magic/class_d_audio_amplifier/comparator/comparator_post.spice
.include /home/eda/magic/class_d_audio_amplifier/dead_time/dead_time_post.spice
.include /home/eda/magic/class_d_audio_amplifier/output_driver/output_driver_post_r.spice
.include /home/eda/magic/class_d_audio_amplifier/integrator/integrator_post.spice
.include /home/eda/magic/class_d_audio_amplifier/biasing_network.spice
* Resistor\\\\$::SKYWATER_MODELS\\\\/Capacitor
.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical.spice
.include \\\\$::SKYWATER_MODELS\\\\/models/r+c/res_typical__cap_typical__lin.spice
* Special cells
.include \\\\$::SKYWATER_MODELS\\\\/models/corners/tt/specialized_cells.spice

"
}
C {lab_wire.sym} 1140 -90 0 0 {name=l9 sig_type=std_logic lab=vtriang}
C {vsource.sym} -110 140 0 0 {name=V5 value=0.9}
C {lab_wire.sym} -110 100 0 0 {name=l26 sig_type=std_logic lab=vref}
C {lab_wire.sym} 690 -240 0 1 {name=l1 sig_type=std_logic lab=vin_p}
C {lab_wire.sym} 1070 -320 0 0 {name=l6 sig_type=std_logic lab=vdd}
C {ind.sym} 2200 -230 1 0 {name=L1
m=1
value=28u
footprint=1206
device=inductor}
C {capa.sym} 2250 -190 0 0 {name=C1
m=1
value=1.3u
footprint=1206
device="ceramic capacitor"}
C {res.sym} 1220 -420 1 0 {name=R1
value=200k
footprint=1206
device=resistor
m=1}
C {res.sym} 770 -260 1 0 {name=R3
value=200k
footprint=1206
device=resistor
m=1}
C {lab_wire.sym} 820 -330 0 0 {name=l18 sig_type=std_logic lab=feedback_p}
C {lab_wire.sym} 1410 -230 0 0 {name=l19 sig_type=std_logic lab=vcmp_p}
C {lab_wire.sym} 1350 -270 0 0 {name=l21 sig_type=std_logic lab=vdd}
C {lab_wire.sym} 1270 -250 0 0 {name=l8 sig_type=std_logic lab=error_p}
C {lab_wire.sym} 1070 110 0 0 {name=l24 sig_type=std_logic lab=vdd}
C {lab_wire.sym} 900 180 0 0 {name=l27 sig_type=std_logic lab=vref}
C {res.sym} 1240 390 1 0 {name=R4
value=200k
footprint=1206
device=resistor
m=1}
C {res.sym} 770 140 1 0 {name=R5
value=200k
footprint=1206
device=resistor
m=1}
C {lab_wire.sym} 1340 130 0 0 {name=l38 sig_type=std_logic lab=vdd}
C {ind.sym} 2190 180 3 1 {name=L2
m=1
value=28u
footprint=1206
device=inductor}
C {capa.sym} 2250 210 0 1 {name=C4
m=1
value=1.3u
footprint=1206
device="ceramic capacitor"}
C {res.sym} 2310 20 2 0 {name=R6
value=8
footprint=1206
device=resistor
m=1}
C {lab_wire.sym} 1230 150 0 0 {name=l29 sig_type=std_logic lab=error_n}
C {lab_wire.sym} 830 220 0 0 {name=l30 sig_type=std_logic lab=feedback_n}
C {lab_wire.sym} 1400 170 0 1 {name=l40 sig_type=std_logic lab=vcmp_n}
C {lab_wire.sym} 2260 -230 0 1 {name=l43 sig_type=std_logic lab=audio_p}
C {lab_wire.sym} 2260 180 0 1 {name=l44 sig_type=std_logic lab=audio_n}
C {vsource.sym} -20 140 0 0 {name=V4 value="pulse(0 1.8 0 10n 10n 10 20)"}
C {lab_wire.sym} -20 90 0 0 {name=l16 sig_type=std_logic lab=vdd}
C {lab_wire.sym} 1550 -290 0 0 {name=l17 sig_type=std_logic lab=vdd}
C {lab_wire.sym} 1550 110 0 0 {name=l34 sig_type=std_logic lab=vdd}
C {lab_wire.sym} 1700 160 0 0 {name=l51 sig_type=std_logic lab=vn_p}
C {lab_wire.sym} 1710 180 0 0 {name=l52 sig_type=std_logic lab=vn_n}
C {lab_wire.sym} 380 -80 0 0 {name=l36 sig_type=std_logic lab=vbias3}
C {lab_wire.sym} 380 -20 0 0 {name=l56 sig_type=std_logic lab=vref}
C {lab_wire.sym} 510 -100 0 0 {name=l57 sig_type=std_logic lab=vdd}
C {lab_wire.sym} 910 -260 0 0 {name=l3 sig_type=std_logic lab=vbias5}
C {lab_wire.sym} 900 160 0 0 {name=l14 sig_type=std_logic lab=vbias6}
C {lab_wire.sym} 1280 -210 0 0 {name=l20 sig_type=std_logic lab=vbias7}
C {lab_wire.sym} 860 -80 0 0 {name=l45 sig_type=std_logic lab=vbias2}
C {lab_wire.sym} 860 -60 0 0 {name=l46 sig_type=std_logic lab=vref}
C {lab_wire.sym} 1020 -60 0 1 {name=l60 sig_type=std_logic lab=vsquare}
C {lab_wire.sym} 1260 190 0 0 {name=l61 sig_type=std_logic lab=vbias8}
C {gnd.sym} -20 200 0 0 {name=l63 lab=GND}
C {gnd.sym} -110 210 0 0 {name=l2 lab=GND}
C {gnd.sym} 190 40 0 0 {name=l4 lab=GND}
C {gnd.sym} 510 10 0 0 {name=l5 lab=GND}
C {gnd.sym} 1070 -180 0 0 {name=l11 lab=GND}
C {gnd.sym} 1350 -180 0 0 {name=l13 lab=GND}
C {gnd.sym} 1550 -170 0 0 {name=l22 lab=GND}
C {gnd.sym} 1550 230 0 0 {name=l41 lab=GND}
C {gnd.sym} 1340 220 0 0 {name=l42 lab=GND}
C {gnd.sym} 1070 210 0 0 {name=l48 lab=GND}
C {gnd.sym} 2250 260 0 0 {name=l55 lab=GND}
C {gnd.sym} 2250 -140 0 0 {name=l58 lab=GND}
C {lab_wire.sym} 860 -100 0 0 {name=l32 sig_type=std_logic lab=vbias1}
C {lab_wire.sym} 380 -60 0 0 {name=l35 sig_type=std_logic lab=vbias4}
C {vsource.sym} 740 -90 0 0 {name=V2 value=1.8}
C {gnd.sym} 740 -40 0 0 {name=l47 lab=GND}
C {lab_wire.sym} 680 140 0 1 {name=l23 sig_type=std_logic lab=vin_n}
C {src/output_driver/output_driver_post.sym} 1910 -10 0 0 {name=x9}
C {lab_wire.sym} 1720 -240 0 1 {name=l15 sig_type=std_logic lab=vp_p}
C {lab_wire.sym} 1700 -190 0 1 {name=l25 sig_type=std_logic lab=vp_n}
C {vsource.sym} 1800 -230 0 0 {name=V3 value=1.8}
C {gnd.sym} 1800 -150 0 0 {name=l28 lab=GND}
C {gnd.sym} 1890 70 0 0 {name=l31 lab=GND}
C {lab_wire.sym} 2090 -230 0 1 {name=l33 sig_type=std_logic lab=out_p}
C {lab_wire.sym} 2100 180 0 1 {name=l37 sig_type=std_logic lab=out_n}
C {lab_wire.sym} 910 -240 0 0 {name=l7 sig_type=std_logic lab=vref}
C {gnd.sym} 940 0 0 0 {name=l12 lab=GND}
C {src/dead_time/dead_time_post.sym} 1480 -250 0 0 {name=x7}
C {src/dead_time/dead_time_post.sym} 1480 150 0 0 {name=x8}
C {src/comparator/comparator_post.sym} 1300 -250 0 0 {name=x5}
C {src/comparator/comparator_post.sym} 1290 150 0 0 {name=x6}
C {src/integrator/integrator_post.sym} 950 -260 0 0 {name=x3}
C {src/integrator/integrator_post.sym} 950 160 0 0 {name=x4}
C {src/S_to_D/S_to_D_revised_post.sym} 390 -70 0 0 {name=x1}
C {src/triangle/triangle_revised_post.sym} 870 -80 0 0 {name=x2}
C {src/biasing_network/biasing_network.sym} 430 460 0 0 {name=x10}
C {gnd.sym} 480 610 0 0 {name=l10 lab=GND}
C {res.sym} 480 250 2 0 {name=R2
value=83k
footprint=1206
device=resistor
m=1}
C {lab_wire.sym} 480 200 0 0 {name=l39 sig_type=std_logic lab=vdd}
C {lab_wire.sym} 630 390 0 0 {name=l49 sig_type=std_logic lab=vbias1}
C {lab_wire.sym} 630 410 0 0 {name=l50 sig_type=std_logic lab=vbias2}
C {lab_wire.sym} 630 430 0 0 {name=l53 sig_type=std_logic lab=vbias3}
C {lab_wire.sym} 630 450 0 0 {name=l54 sig_type=std_logic lab=vbias4}
C {lab_wire.sym} 630 470 0 0 {name=l59 sig_type=std_logic lab=vbias5}
C {lab_wire.sym} 630 490 0 0 {name=l62 sig_type=std_logic lab=vbias6}
C {lab_wire.sym} 630 510 0 0 {name=l64 sig_type=std_logic lab=vbias7}
C {lab_wire.sym} 630 530 0 0 {name=l65 sig_type=std_logic lab=vbias8}