)]}'
{
  "log": [
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        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Wed Dec 29 03:44:19 2021 -0800"
      },
      "committer": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Wed Dec 29 03:44:19 2021 -0800"
      },
      "message": "final gds oasis\n"
    },
    {
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        "email": "hadirkhan10@gmail.com",
        "time": "Mon Dec 27 23:05:39 2021 -0800"
      },
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        "name": "hadirkhan10",
        "email": "hadirkhan10@gmail.com",
        "time": "Mon Dec 27 23:05:39 2021 -0800"
      },
      "message": "added all the sp srams with memory maps and interfaced them through wishbone\n"
    },
    {
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        "time": "Mon Dec 27 23:04:50 2021 -0800"
      },
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        "name": "hadirkhan10",
        "email": "hadirkhan10@gmail.com",
        "time": "Mon Dec 27 23:04:50 2021 -0800"
      },
      "message": "modified the tests for including other srams\n"
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    {
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        "time": "Thu Dec 23 17:14:05 2021 -0800"
      },
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        "name": "hadirkhan10",
        "email": "hadirkhan10@gmail.com",
        "time": "Thu Dec 23 17:14:05 2021 -0800"
      },
      "message": "corrected a comment\n"
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    {
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        "time": "Thu Dec 23 17:11:54 2021 -0800"
      },
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        "name": "hadirkhan10",
        "email": "hadirkhan10@gmail.com",
        "time": "Thu Dec 23 17:11:54 2021 -0800"
      },
      "message": "added a bus ram mux and created the functionality to test two srams through wishbone with different address mappings\n"
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    {
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        "time": "Thu Dec 23 17:10:24 2021 -0800"
      },
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        "email": "hadirkhan10@gmail.com",
        "time": "Thu Dec 23 17:10:24 2021 -0800"
      },
      "message": "modified the testing to test two srams with different address mappings\n"
    },
    {
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        "email": "hadirkhan10@gmail.com",
        "time": "Wed Dec 22 17:33:37 2021 -0800"
      },
      "committer": {
        "name": "hadirkhan10",
        "email": "hadirkhan10@gmail.com",
        "time": "Wed Dec 22 17:33:37 2021 -0800"
      },
      "message": "changed the base address for sram 8\n"
    },
    {
      "commit": "db617f9dc2bdcca267463ab57feeee661c2085fd",
      "tree": "b6bf37b53338e3b5ad49b192e1119347fb7e8710",
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        "email": "hadirkhan10@gmail.com",
        "time": "Tue Dec 21 22:49:05 2021 -0800"
      },
      "committer": {
        "name": "hadirkhan10",
        "email": "hadirkhan10@gmail.com",
        "time": "Tue Dec 21 22:49:05 2021 -0800"
      },
      "message": "aligned the sram data output with wishbone ack\n"
    },
    {
      "commit": "e598c9ad5499e350c637a72884bb93d5f8992b4a",
      "tree": "de7abef707b7b45fabc5ee2aeac4e1de48cfeb79",
      "parents": [
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      "author": {
        "name": "hadirkhan10",
        "email": "hadirkhan10@gmail.com",
        "time": "Tue Dec 21 22:44:06 2021 -0800"
      },
      "committer": {
        "name": "hadirkhan10",
        "email": "hadirkhan10@gmail.com",
        "time": "Tue Dec 21 22:44:06 2021 -0800"
      },
      "message": "added more test cases and made the test self-checking\n"
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    {
      "commit": "45be369df9c9d4d93680797c4543a7d234f81805",
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        "email": "hadirkhan10@gmail.com",
        "time": "Tue Dec 21 16:12:47 2021 -0800"
      },
      "committer": {
        "name": "hadirkhan10",
        "email": "hadirkhan10@gmail.com",
        "time": "Tue Dec 21 16:12:47 2021 -0800"
      },
      "message": "created a testbench to write/read to a single sram using wishbone\n"
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    {
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        "time": "Tue Dec 21 16:11:05 2021 -0800"
      },
      "committer": {
        "name": "hadirkhan10",
        "email": "hadirkhan10@gmail.com",
        "time": "Tue Dec 21 16:11:05 2021 -0800"
      },
      "message": "added changes to use wishbone interface for providing csb for single sram 8 and made sure other tests pass\n"
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    {
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        "email": "hadirkhan10@gmail.com",
        "time": "Sun Dec 19 23:08:52 2021 -0800"
      },
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        "name": "hadirkhan10",
        "email": "hadirkhan10@gmail.com",
        "time": "Sun Dec 19 23:08:52 2021 -0800"
      },
      "message": "added some functionality to read a single sram through wishbone. Testing is remaining\n"
    },
    {
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        "email": "hadirkhan10@gmail.com",
        "time": "Sun Dec 19 23:08:02 2021 -0800"
      },
      "committer": {
        "name": "hadirkhan10",
        "email": "hadirkhan10@gmail.com",
        "time": "Sun Dec 19 23:08:02 2021 -0800"
      },
      "message": "created a wishbone wrapper for openram\n"
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    {
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        "email": "hadirkhan10@gmail.com",
        "time": "Sun Dec 19 23:07:21 2021 -0800"
      },
      "committer": {
        "name": "hadirkhan10",
        "email": "hadirkhan10@gmail.com",
        "time": "Sun Dec 19 23:07:21 2021 -0800"
      },
      "message": "added wishbone_wrapper as another source file\n"
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    {
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        "email": "hadirkhan10@gmail.com",
        "time": "Sat Dec 18 22:51:13 2021 -0800"
      },
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        "name": "hadirkhan10",
        "email": "hadirkhan10@gmail.com",
        "time": "Sat Dec 18 22:51:13 2021 -0800"
      },
      "message": "made the clock select multiplexer compatible to take more than two input sources for future wishbone clock\n"
    },
    {
      "commit": "5e4df0dfda5fa6c50cbf1ec601d6ce3ca5bf8a4d",
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        "email": "hadirkhan10@gmail.com",
        "time": "Fri Dec 17 20:57:36 2021 -0800"
      },
      "committer": {
        "name": "hadirkhan10",
        "email": "hadirkhan10@gmail.com",
        "time": "Fri Dec 17 20:57:36 2021 -0800"
      },
      "message": "resolved the merge conflicts and made the la_test working again\n"
    },
    {
      "commit": "14ef1c5901ca745d354cb6edfeafe00a2b5f6434",
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        "email": "hadirkhan10@gmail.com",
        "time": "Fri Dec 17 20:40:20 2021 -0800"
      },
      "committer": {
        "name": "hadirkhan10",
        "email": "hadirkhan10@gmail.com",
        "time": "Fri Dec 17 20:40:20 2021 -0800"
      },
      "message": "changed the pins io pins for the la test to work properly\n"
    },
    {
      "commit": "ce65f0064ab72841112285bce9212c6673d290ce",
      "tree": "ab356ecc3789da6559925c6d1360f485c082189a",
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      "author": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Thu Dec 16 13:36:54 2021 -0800"
      },
      "committer": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Thu Dec 16 13:36:54 2021 -0800"
      },
      "message": "replaced decap cells with modified versions\n"
    },
    {
      "commit": "ea1263c18cbe88f2c9fd330c261b7d5bec1ed560",
      "tree": "9408ddbedaefb216ad423e6391618896ef06210b",
      "parents": [
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      "author": {
        "name": "mrg",
        "email": "mrg@ucsc.edu",
        "time": "Wed Dec 15 09:37:40 2021 -0800"
      },
      "committer": {
        "name": "mrg",
        "email": "mrg@ucsc.edu",
        "time": "Wed Dec 15 09:37:40 2021 -0800"
      },
      "message": "Manually edit areaid.mem, m3 spacing errors.\n"
    },
    {
      "commit": "7956e1befd2c924e6141e18d53b22168c98aa811",
      "tree": "98f34c0639d44131fe451685e099d7a1a1213142",
      "parents": [
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      "author": {
        "name": "mrg",
        "email": "mrg@ucsc.edu",
        "time": "Wed Dec 15 09:36:56 2021 -0800"
      },
      "committer": {
        "name": "mrg",
        "email": "mrg@ucsc.edu",
        "time": "Wed Dec 15 09:36:56 2021 -0800"
      },
      "message": "Fix ntap fill spacing\n"
    },
    {
      "commit": "71aca529446455fbaf79f7e79d6243fbfe297495",
      "tree": "ca63c231baa0747e020217a86e65ba631c92059c",
      "parents": [
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      "author": {
        "name": "mrg",
        "email": "mrg@ucsc.edu",
        "time": "Tue Dec 14 14:10:22 2021 -0800"
      },
      "committer": {
        "name": "mrg",
        "email": "mrg@ucsc.edu",
        "time": "Tue Dec 14 14:10:22 2021 -0800"
      },
      "message": "Fix FEOL (npc, nsdm, psdm) errors in the port_address of SP SRAMs.\n"
    },
    {
      "commit": "41ce5f51de459ec85e3d4dd6f3e8fc578f7245ad",
      "tree": "a94492a579f37f4a6c64b43c82974bdc99a0d671",
      "parents": [
        "e3500a4b64a5fa0544437bd2afce8537361460f3"
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      "author": {
        "name": "mrg",
        "email": "mrg@ucsc.edu",
        "time": "Tue Dec 14 11:32:16 2021 -0800"
      },
      "committer": {
        "name": "mrg",
        "email": "mrg@ucsc.edu",
        "time": "Tue Dec 14 11:32:16 2021 -0800"
      },
      "message": "Update with uniquified sp SRAMs\n"
    },
    {
      "commit": "e3500a4b64a5fa0544437bd2afce8537361460f3",
      "tree": "71ffac25f174d9ecfa10a92c5b4be9264d31974e",
      "parents": [
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      "author": {
        "name": "mrg",
        "email": "mrg@ucsc.edu",
        "time": "Sat Dec 04 12:45:51 2021 -0800"
      },
      "committer": {
        "name": "mrg",
        "email": "mrg@ucsc.edu",
        "time": "Sat Dec 04 12:45:51 2021 -0800"
      },
      "message": "Replace 1rw macros with bitline fixes.\n"
    },
    {
      "commit": "860d08b3a556704e4f88ebba3747c6f4a4f55790",
      "tree": "db99c268bc4ab89842e67e0a95ad56aaee58384a",
      "parents": [
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        "name": "mrg",
        "email": "mrg@ucsc.edu",
        "time": "Mon Nov 15 15:54:05 2021 -0800"
      },
      "committer": {
        "name": "mrg",
        "email": "mrg@ucsc.edu",
        "time": "Mon Nov 15 15:54:05 2021 -0800"
      },
      "message": "Pre-check mostly passes except:\n\nnwell.pin over dnwell.drawing\nMagic DRC without SRAM maglef files\n"
    },
    {
      "commit": "47fcca041db7c772d3da4aad2735d56f190ccae3",
      "tree": "80e6a5d10cf10fcaae1616e3896818a8cc845b39",
      "parents": [
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      "author": {
        "name": "mrg",
        "email": "mrg@ucsc.edu",
        "time": "Mon Nov 15 13:41:25 2021 -0800"
      },
      "committer": {
        "name": "mrg",
        "email": "mrg@ucsc.edu",
        "time": "Mon Nov 15 13:41:25 2021 -0800"
      },
      "message": "Fix small DRC errors in sky130_sram_8kbyte_1rw1r_32x2048_8\n"
    },
    {
      "commit": "19c84ba0d5ef3d51122127cba8f38dee99f10983",
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        "email": "mrg@ucsc.edu",
        "time": "Mon Nov 15 10:21:35 2021 -0800"
      },
      "committer": {
        "name": "mrg",
        "email": "mrg@ucsc.edu",
        "time": "Mon Nov 15 10:21:35 2021 -0800"
      },
      "message": "Final tape-out version possibly\n"
    },
    {
      "commit": "42f370a85bc22dfc1eeeb9f1eeb4d650ec50f547",
      "tree": "02863eab06b8e5f0c42b423de74737fd86494620",
      "parents": [
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      "author": {
        "name": "mrg",
        "email": "mrg@ucsc.edu",
        "time": "Sun Nov 14 16:44:02 2021 -0800"
      },
      "committer": {
        "name": "mrg",
        "email": "mrg@ucsc.edu",
        "time": "Sun Nov 14 16:44:02 2021 -0800"
      },
      "message": "Add uniquify shell script\n"
    },
    {
      "commit": "54ac4b4a03ef640d9bf4f0a3c303f3b3b5d64f93",
      "tree": "1292f5b025e5e330c16ad8d86a05c61fc119ad8b",
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      "author": {
        "name": "mrg",
        "email": "mrg@ucsc.edu",
        "time": "Sun Nov 14 16:39:43 2021 -0800"
      },
      "committer": {
        "name": "mrg",
        "email": "mrg@ucsc.edu",
        "time": "Sun Nov 14 16:39:43 2021 -0800"
      },
      "message": "Manually copy gds/mag/maglef\n"
    },
    {
      "commit": "fa0ec72f91cf2d6c749f698f64a528eeb4c5fc56",
      "tree": "b71dcf65cffb167e0731dcef11932f2ae80dee6f",
      "parents": [
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        "name": "mrg",
        "email": "mrg@ucsc.edu",
        "time": "Sun Nov 14 16:02:56 2021 -0800"
      },
      "committer": {
        "name": "mrg",
        "email": "mrg@ucsc.edu",
        "time": "Sun Nov 14 16:02:56 2021 -0800"
      },
      "message": "Pre-tapeout version\n"
    },
    {
      "commit": "98ac71abbecd77dc96a83afb879c3dbad02075f4",
      "tree": "d4aa56533ef9912bb58d050c2e547ffa26277a77",
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      "author": {
        "name": "mrg",
        "email": "mrg@ucsc.edu",
        "time": "Sun Nov 14 16:02:36 2021 -0800"
      },
      "committer": {
        "name": "mrg",
        "email": "mrg@ucsc.edu",
        "time": "Sun Nov 14 16:02:36 2021 -0800"
      },
      "message": "Delete user_proj_example\n"
    },
    {
      "commit": "f9bf1d374d4ed55de36ffac6140d4cff3d8397a8",
      "tree": "c699e28523ebbc18471c7fedb7646c274f2717cb",
      "parents": [
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      "author": {
        "name": "mrg",
        "email": "mrg@ucsc.edu",
        "time": "Sat Nov 13 16:01:08 2021 -0800"
      },
      "committer": {
        "name": "mrg",
        "email": "mrg@ucsc.edu",
        "time": "Sat Nov 13 16:01:08 2021 -0800"
      },
      "message": "MPW3 initial completing design.\n"
    },
    {
      "commit": "b7132b8562763b2ba090c77958b9d4635a306849",
      "tree": "29a72f4899e91e0f0a57559e84ee6891e0197688",
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        "name": "mrg",
        "email": "mrg@ucsc.edu",
        "time": "Thu Nov 11 07:54:12 2021 -0800"
      },
      "committer": {
        "name": "mrg",
        "email": "mrg@ucsc.edu",
        "time": "Thu Nov 11 07:54:12 2021 -0800"
      },
      "message": "Add back clocks and fix verilog path.\n"
    },
    {
      "commit": "e194f83b982be3d69d4fb75594c73ad7a7e2c7fc",
      "tree": "442d447fced81b7ebaab96219fccf9d05ceaa24e",
      "parents": [
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}