)]}'
{
  "commit": "ebf94d6c47bc99a5aa3277d9c6ce626a600d31e0",
  "tree": "c1e0a34827f8b7cc26aab9bccfa00101d86552fa",
  "parents": [
    "d2e307963e56dbb570872b287eccb7404d264a0a"
  ],
  "author": {
    "name": "hadirkhan10",
    "email": "hadirkhan10@gmail.com",
    "time": "Tue Dec 21 16:11:05 2021 -0800"
  },
  "committer": {
    "name": "hadirkhan10",
    "email": "hadirkhan10@gmail.com",
    "time": "Tue Dec 21 16:11:05 2021 -0800"
  },
  "message": "added changes to use wishbone interface for providing csb for single sram 8 and made sure other tests pass\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "2d03699003c503289efe268885c0fe44a0c58074",
      "old_mode": 33188,
      "old_path": "verilog/rtl/openram_testchip.v",
      "new_id": "cce0713f459372db6be32bd5d35240e0d16c2c81",
      "new_mode": 33188,
      "new_path": "verilog/rtl/openram_testchip.v"
    },
    {
      "type": "modify",
      "old_id": "2b3f08b9831f36a2c24aab469bc5e3327c9d9836",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project_wrapper.v",
      "new_id": "bfdfc21182f19fc871686ebca2260476b002ce0b",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_project_wrapper.v"
    }
  ]
}