diff --git a/verilog/dv/wb_test/wb_test.c b/verilog/dv/wb_test/wb_test.c
index 67e0f1f..1ccc88b 100644
--- a/verilog/dv/wb_test/wb_test.c
+++ b/verilog/dv/wb_test/wb_test.c
@@ -22,7 +22,7 @@
 // Caravel allows user project to use 0x30xx_xxxx address space on Wishbone bus
 // OpenRAM
 // 0x30c0_0000 till 30c0_03ff -> 256 Words of OpenRAM (1024 Bytes)
-#define OPENRAM_BASE_ADDRESS		0x30c00000
+#define OPENRAM_BASE_ADDRESS		0x30000000
 #define OPENRAM_SIZE_DWORDS		256ul			
 #define OPENRAM_SIZE_BYTES		(4ul * OPENRAM_SIZE_DWORDS)
 #define OPENRAM_ADDRESS_MASK		(OPENRAM_SIZE_BYTES - 1)
diff --git a/verilog/rtl/wishbone_wrapper.v b/verilog/rtl/wishbone_wrapper.v
index e5ffb3f..e81eb2a 100644
--- a/verilog/rtl/wishbone_wrapper.v
+++ b/verilog/rtl/wishbone_wrapper.v
@@ -2,7 +2,7 @@
 
 module wishbone_wrapper
 #(
-	parameter BASE_ADDR = 32'h30c0_0000,
+	parameter BASE_ADDR = 32'h3000_0000,
     parameter ADDR_WIDTH = 8
 )
 (