)]}'
{
  "commit": "db617f9dc2bdcca267463ab57feeee661c2085fd",
  "tree": "b6bf37b53338e3b5ad49b192e1119347fb7e8710",
  "parents": [
    "e598c9ad5499e350c637a72884bb93d5f8992b4a"
  ],
  "author": {
    "name": "hadirkhan10",
    "email": "hadirkhan10@gmail.com",
    "time": "Tue Dec 21 22:49:05 2021 -0800"
  },
  "committer": {
    "name": "hadirkhan10",
    "email": "hadirkhan10@gmail.com",
    "time": "Tue Dec 21 22:49:05 2021 -0800"
  },
  "message": "aligned the sram data output with wishbone ack\n",
  "tree_diff": [
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      "new_path": "verilog/rtl/openram_testchip.v"
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}
