)]}'
{
  "commit": "d2e307963e56dbb570872b287eccb7404d264a0a",
  "tree": "5653de2cb07d5dbe59b6d7a154a0a79c7af51fac",
  "parents": [
    "1e5d85babafc69de28dc9578989be1934598c4e2"
  ],
  "author": {
    "name": "hadirkhan10",
    "email": "hadirkhan10@gmail.com",
    "time": "Sun Dec 19 23:08:52 2021 -0800"
  },
  "committer": {
    "name": "hadirkhan10",
    "email": "hadirkhan10@gmail.com",
    "time": "Sun Dec 19 23:08:52 2021 -0800"
  },
  "message": "added some functionality to read a single sram through wishbone. Testing is remaining\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "a8cc3d95e1f9b4eb1b2c0c5f339741c3c50c8625",
      "old_mode": 33188,
      "old_path": "verilog/rtl/openram_testchip.v",
      "new_id": "2d03699003c503289efe268885c0fe44a0c58074",
      "new_mode": 33188,
      "new_path": "verilog/rtl/openram_testchip.v"
    },
    {
      "type": "modify",
      "old_id": "22a831553f0ef259b30761fb96cbea04b4d6dc77",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project_wrapper.v",
      "new_id": "2b3f08b9831f36a2c24aab469bc5e3327c9d9836",
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      "new_path": "verilog/rtl/user_project_wrapper.v"
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}