diff --git a/verilog/dv/wb_test/wb_test.c b/verilog/dv/wb_test/wb_test.c
index b60d51a..3b07c2e 100644
--- a/verilog/dv/wb_test/wb_test.c
+++ b/verilog/dv/wb_test/wb_test.c
@@ -34,11 +34,26 @@
 #define SRAM9_ADDRESS_MASK		(SRAM9_SIZE_BYTES - 1)
 #define SRAM9_MEM(offset)		(*(volatile uint32_t*)(SRAM9_BASE_ADDRESS + (offset & SRAM9_ADDRESS_MASK)))
 
+#define SRAM10_BASE_ADDRESS		0x30000c00
+#define SRAM10_SIZE_DWORDS		1024ul			
+#define SRAM10_SIZE_BYTES		(4ul * SRAM10_SIZE_DWORDS)
+#define SRAM10_ADDRESS_MASK		(SRAM10_SIZE_BYTES - 1)
+#define SRAM10_MEM(offset)		(*(volatile uint32_t*)(SRAM10_BASE_ADDRESS + (offset & SRAM10_ADDRESS_MASK)))
 
+#define SRAM11_BASE_ADDRESS		0x30001c00
+#define SRAM11_SIZE_DWORDS		1024ul			
+#define SRAM11_SIZE_BYTES		(4ul * SRAM11_SIZE_DWORDS)
+#define SRAM11_ADDRESS_MASK		(SRAM11_SIZE_BYTES - 1)
+#define SRAM11_MEM(offset)		(*(volatile uint32_t*)(SRAM11_BASE_ADDRESS + (offset & SRAM11_ADDRESS_MASK)))
+
+#define SRAM12_BASE_ADDRESS		0x30002c00
+#define SRAM12_SIZE_DWORDS		2048ul			
+#define SRAM12_SIZE_BYTES		(4ul * SRAM12_SIZE_DWORDS)
+#define SRAM12_ADDRESS_MASK		(SRAM12_SIZE_BYTES - 1)
+#define SRAM12_MEM(offset)		(*(volatile uint32_t*)(SRAM12_BASE_ADDRESS + (offset & SRAM12_ADDRESS_MASK)))
 
 void main()
 {
-	unsigned int address = 0;
 
 	/* 
 	IO Control Registers
@@ -72,6 +87,9 @@
 	reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
 	reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
 	reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
+	reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
 	/* Apply configuration */
 	reg_mprj_xfer = 1;
 	while (reg_mprj_xfer == 1);
@@ -82,13 +100,28 @@
 
 	SRAM8_MEM(0) = 0xdeadbeef;
 	SRAM9_MEM(0) = 0xbeefdead;
+	SRAM10_MEM(0) = 0xbeef1234;
+	SRAM11_MEM(0) = 0xbeef5678;
+	SRAM12_MEM(0) = 0xbeef9abc;
+
 	SRAM8_MEM(4) = 0xdeadbee0;
 	SRAM9_MEM(4) = 0xbee0dead;
+	SRAM10_MEM(4) = 0xbee1dead;
+	SRAM11_MEM(4) = 0xbee2dead;
+	SRAM12_MEM(4) = 0xbee3dead;
+
 	SRAM8_MEM(8) = 0xffffffff;
 	SRAM9_MEM(8) = 0x12345678;
+	SRAM10_MEM(8) = 0xabababab;
+	SRAM11_MEM(8) = 0xcdcdcdcd;
+	SRAM12_MEM(8) = 0xefefefef;
+
 	SRAM8_MEM(12) = 0xdeaddead;
 	SRAM9_MEM(12) = 0x10101010;
-	// this is not working because the data is correct but sp rams send an additional x which makes this fail
+	SRAM10_MEM(12) = 0x20202020;
+	SRAM11_MEM(12) = 0x30303030;
+	SRAM12_MEM(12) = 0x40404040;
+
 	if (SRAM8_MEM(0) != 0xdeadbeef) {
 		// send an error signal to the testbench
 		reg_mprj_datal = 0x20000000;
@@ -107,7 +140,6 @@
 	}
 
 
-	// this is not working because the data is correct but sp rams send an additional x which makes this fail
 	if (SRAM9_MEM(0) != 0xbeefdead) {
 		// send an error signal to the testbench
 		reg_mprj_datal = 0x40000000;
@@ -125,6 +157,57 @@
 		reg_mprj_datal = 0x40000000;
 	}
 
+	if (SRAM10_MEM(0) != 0xbeef1234) {
+		// send an error signal to the testbench
+		reg_mprj_datal = 0x80000000;
+	}
+	if (SRAM10_MEM(4) != 0xbee1dead) {
+		// send an error signal to the testbench
+		reg_mprj_datal = 0x80000000;
+	}
+	if (SRAM10_MEM(8) != 0xabababab) {
+		// send an error signal to the testbench
+		reg_mprj_datal = 0x80000000;
+	}
+	if (SRAM10_MEM(12) != 0x20202020) {
+		// send an error signal to the testbench
+		reg_mprj_datal = 0x80000000;
+	}
+
+	if (SRAM11_MEM(0) != 0xbeef5678) {
+		// send an error signal to the testbench
+		reg_mprj_datah = 0x00000001;
+	}
+	if (SRAM11_MEM(4) != 0xbee2dead) {
+		// send an error signal to the testbench
+		reg_mprj_datah = 0x00000001;
+	}
+	if (SRAM11_MEM(8) != 0xcdcdcdcd) {
+		// send an error signal to the testbench
+		reg_mprj_datah = 0x00000001;
+	}
+	if (SRAM11_MEM(12) != 0x30303030) {
+		// send an error signal to the testbench
+		reg_mprj_datah = 0x00000001;
+	}
+
+	if (SRAM12_MEM(0) != 0xbeef9abc) {
+		// send an error signal to the testbench
+		reg_mprj_datah = 0x00000002;
+	}
+	if (SRAM12_MEM(4) != 0xbee3dead) {
+		// send an error signal to the testbench
+		reg_mprj_datah = 0x00000002;
+	}
+	if (SRAM12_MEM(8) != 0xefefefef) {
+		// send an error signal to the testbench
+		reg_mprj_datah = 0x00000002;
+	}
+	if (SRAM12_MEM(12) != 0x40404040) {
+		// send an error signal to the testbench
+		reg_mprj_datah = 0x00000002;
+	}
+
 	reg_mprj_datal = 0x00000000;			
 }
 
diff --git a/verilog/dv/wb_test/wb_test_tb.v b/verilog/dv/wb_test/wb_test_tb.v
index a401540..2dce6bb 100644
--- a/verilog/dv/wb_test/wb_test_tb.v
+++ b/verilog/dv/wb_test/wb_test_tb.v
@@ -91,8 +91,23 @@
 		$display($time, " Data mismatch while reading data from SRAM 9!"); 
 	end
 
+	initial begin
+		wait (mprj_io_31 == 1'b1);
+		$display($time, " Data mismatch while reading data from SRAM 10!"); 
+	end
+
+	initial begin
+		wait (mprj_io_32 == 1'b1);
+		$display($time, " Data mismatch while reading data from SRAM 11!"); 
+	end
+
+	initial begin
+		wait (mprj_io_33 == 1'b1);
+		$display($time, " Data mismatch while reading data from SRAM 12!"); 
+	end
+
    initial begin
-      #5000000
+      #1000000
       $display("Timeout");
       $finish;
    end