)]}'
{
  "commit": "8198ddb83e9724bd3bb65b95faa90fe950152e13",
  "tree": "6e0951232c8ed684a15612399f3d3d34398b4dfc",
  "parents": [
    "7e0b07b20dfe946a18ddb020cbc5ac4a87a6037e"
  ],
  "author": {
    "name": "hadirkhan10",
    "email": "hadirkhan10@gmail.com",
    "time": "Thu Dec 23 17:11:54 2021 -0800"
  },
  "committer": {
    "name": "hadirkhan10",
    "email": "hadirkhan10@gmail.com",
    "time": "Thu Dec 23 17:11:54 2021 -0800"
  },
  "message": "added a bus ram mux and created the functionality to test two srams through wishbone with different address mappings\n",
  "tree_diff": [
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      "new_path": "verilog/rtl/openram_testchip.v"
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    {
      "type": "add",
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      "new_path": "verilog/rtl/wishbone_ram_mux.v"
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}