)]}'
{
  "commit": "7ca845bd8b32fdb71ba76d60bf09991bfb6091f4",
  "tree": "68005780db3eb05aaa234674c35f086e1622961f",
  "parents": [
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  "author": {
    "name": "hadirkhan10",
    "email": "hadirkhan10@gmail.com",
    "time": "Thu Dec 23 17:14:05 2021 -0800"
  },
  "committer": {
    "name": "hadirkhan10",
    "email": "hadirkhan10@gmail.com",
    "time": "Thu Dec 23 17:14:05 2021 -0800"
  },
  "message": "corrected a comment\n",
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      "old_mode": 33188,
      "old_path": "verilog/rtl/wishbone_ram_mux.v",
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}