)]}'
{
  "commit": "6bedf5e63920a8c50b3c811e43f09fed72f12bce",
  "tree": "e38b32e208315c5412b230c696e2a86253cd4ed6",
  "parents": [
    "b218c88bb94f5f762b15e839af046fd430e3008f"
  ],
  "author": {
    "name": "hadirkhan10",
    "email": "hadirkhan10@gmail.com",
    "time": "Mon Dec 27 23:05:39 2021 -0800"
  },
  "committer": {
    "name": "hadirkhan10",
    "email": "hadirkhan10@gmail.com",
    "time": "Mon Dec 27 23:05:39 2021 -0800"
  },
  "message": "added all the sp srams with memory maps and interfaced them through wishbone\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "e159acd301d0eb59c22850237496f0bec198bfce",
      "old_mode": 33188,
      "old_path": "verilog/rtl/openram_testchip.v",
      "new_id": "94b56e0804ab76908cd8bd2cb571df75c6485bde",
      "new_mode": 33188,
      "new_path": "verilog/rtl/openram_testchip.v"
    },
    {
      "type": "modify",
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      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project_wrapper.v",
      "new_id": "e8ffaee1094f5a913a5083ccd951baa05ef82866",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_project_wrapper.v"
    },
    {
      "type": "modify",
      "old_id": "642199253f9933cf74c8a661ff609f04887adb1c",
      "old_mode": 33188,
      "old_path": "verilog/rtl/wishbone_ram_mux.v",
      "new_id": "5c00ea3a02135686da36dceb9e35c3ab782add90",
      "new_mode": 33188,
      "new_path": "verilog/rtl/wishbone_ram_mux.v"
    }
  ]
}