)]}'
{
  "commit": "47c4dee655fdaa5d564c0f019976f228f0664279",
  "tree": "b3608784ef9e6f8a780f0be3ef7eadcd1e406a05",
  "parents": [
    "1de29c798d70738b1e79bbe4bd2b31917044bf9e"
  ],
  "author": {
    "name": "mrg",
    "email": "mrg@ucsc.edu",
    "time": "Tue Nov 09 14:04:11 2021 -0800"
  },
  "committer": {
    "name": "mrg",
    "email": "mrg@ucsc.edu",
    "time": "Tue Nov 09 14:04:11 2021 -0800"
  },
  "message": "Bug in connection of SRAM12 output.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "089f2ea3082d6b55ef73c325aaf97d0767f5945e",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project_wrapper.v",
      "new_id": "58b91276bb0901d03d1c0f6fb78eba93f6eb12e9",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_project_wrapper.v"
    }
  ]
}