)]}'
{
  "commit": "2e21655ab78215bf4bbc9611ce5ae4b9e4e656c8",
  "tree": "16927a21ae1eeee58f3e5e0eac52592952b3666e",
  "parents": [
    "4c19d4c8db7437c0fa5714f4e3faba56c89b5ae2"
  ],
  "author": {
    "name": "mrg",
    "email": "mrg@ucsc.edu",
    "time": "Sun Nov 07 07:34:40 2021 -0800"
  },
  "committer": {
    "name": "mrg",
    "email": "mrg@ucsc.edu",
    "time": "Sun Nov 07 07:34:40 2021 -0800"
  },
  "message": "Add missing disconnected wire declaration\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "acf0976fc350396d4da13e18758447b63c8892e0",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project_wrapper.v",
      "new_id": "089f2ea3082d6b55ef73c325aaf97d0767f5945e",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_project_wrapper.v"
    }
  ]
}