)]}'
{
  "commit": "1e5d85babafc69de28dc9578989be1934598c4e2",
  "tree": "eb2ab33ba6e70450bc4ec49da56b4df22a4aadf1",
  "parents": [
    "805c9a0728def3bab0f4238c346ef59a7c0386d3"
  ],
  "author": {
    "name": "hadirkhan10",
    "email": "hadirkhan10@gmail.com",
    "time": "Sun Dec 19 23:08:02 2021 -0800"
  },
  "committer": {
    "name": "hadirkhan10",
    "email": "hadirkhan10@gmail.com",
    "time": "Sun Dec 19 23:08:02 2021 -0800"
  },
  "message": "created a wishbone wrapper for openram\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "10e4b3392619e787bc3e51c056e3b6260a7e243b",
      "new_mode": 33188,
      "new_path": "verilog/rtl/wishbone_wrapper.v"
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}