diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
index 796f829..dad8a06 100644
--- a/gds/user_project_wrapper.gds.gz
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ
diff --git a/mag/user_project_wrapper.mag.gz b/mag/user_project_wrapper.mag.gz
index 06a7b07..358fd47 100644
--- a/mag/user_project_wrapper.mag.gz
+++ b/mag/user_project_wrapper.mag.gz
Binary files differ
diff --git a/maglef/user_project_wrapper.mag b/maglef/user_project_wrapper.mag
index 4d04e27..b2faf7b 100644
--- a/maglef/user_project_wrapper.mag
+++ b/maglef/user_project_wrapper.mag
@@ -1,7 +1,7 @@
 magic
 tech sky130A
 magscale 1 2
-timestamp 1636921959
+timestamp 1636989270
 << obsli1 >>
 rect 1104 2159 582820 701777
 << obsm1 >>
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index d10ca8f..5457e34 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -124,3 +124,4 @@
 #set ::env(TAP_DECAP_INSERTION) 0
 # set ::env(CLOCK_TREE_SYNTH) 0
 set ::env(RUN_CVC) 0
+set ::env(MAGIC_DRC_USE_GDS) 0
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index fda9301..98f8adb 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,3h0m6s,-1,574.4084682440848,10.2784,287.2042341220424,0.4,3902.63,2952,0,0,0,0,0,0,0,54,0,-1,-1,1433665,32215,0.0,-18.0,-1,0.0,-1,0.0,-1818.86,-1,0.0,-1,1004048604.0,40815.58,5.7,5.96,1.75,1.85,-1,1315,5517,177,4379,0,0,0,1709,0,0,0,0,0,0,0,4,1128,673,7,5990,96759,0,102749,32.25806451612903,31,30,AREA 0,5,50,1,180,180,0.25,0.25,sky130_fd_sc_hd,4,4
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,3h13m17s,-1,574.4084682440848,10.2784,287.2042341220424,0.4,3902.34,2952,0,0,0,0,0,0,1363,54,0,-1,-1,1433665,32215,0.0,-18.0,-1,0.0,-1,0.0,-1818.86,-1,0.0,-1,1004048604.0,40815.58,5.7,5.96,1.75,1.85,-1,1315,5517,177,4379,0,0,0,1709,0,0,0,0,0,0,0,4,1128,673,7,5990,96759,0,102749,32.25806451612903,31,30,AREA 0,5,50,1,180,180,0.25,0.25,sky130_fd_sc_hd,4,4