diff --git a/verilog/rtl/syntacore_scr1/src/ahb_top.files b/verilog/rtl/syntacore_scr1/src/ahb_top.files
deleted file mode 100644
index 603839e..0000000
--- a/verilog/rtl/syntacore_scr1/src/ahb_top.files
+++ /dev/null
@@ -1,8 +0,0 @@
-top/scr1_dmem_router.sv
-top/scr1_imem_router.sv
-top/scr1_dp_memory.sv
-top/scr1_tcm.sv
-top/scr1_timer.sv
-top/scr1_dmem_ahb.sv
-top/scr1_imem_ahb.sv
-top/scr1_top_ahb.sv
diff --git a/verilog/rtl/syntacore_scr1/src/axi_top.files b/verilog/rtl/syntacore_scr1/src/axi_top.files
deleted file mode 100644
index 24f4b8e..0000000
--- a/verilog/rtl/syntacore_scr1/src/axi_top.files
+++ /dev/null
@@ -1,7 +0,0 @@
-top/scr1_dmem_router.sv
-top/scr1_imem_router.sv
-top/scr1_dp_memory.sv
-top/scr1_tcm.sv
-top/scr1_timer.sv
-top/scr1_mem_axi.sv
-top/scr1_top_axi.sv
\ No newline at end of file
diff --git a/verilog/rtl/syntacore_scr1/src/core.files b/verilog/rtl/syntacore_scr1/src/core.files
deleted file mode 100644
index ca5de45..0000000
--- a/verilog/rtl/syntacore_scr1/src/core.files
+++ /dev/null
@@ -1,21 +0,0 @@
-core/pipeline/scr1_pipe_hdu.sv
-core/pipeline/scr1_pipe_tdu.sv
-core/pipeline/scr1_ipic.sv
-core/pipeline/scr1_pipe_csr.sv
-core/pipeline/scr1_pipe_exu.sv
-core/pipeline/scr1_pipe_ialu.sv
-core/pipeline/scr1_pipe_idu.sv
-core/pipeline/scr1_pipe_ifu.sv
-core/pipeline/scr1_pipe_lsu.sv
-core/pipeline/scr1_pipe_mprf.sv
-core/pipeline/scr1_pipe_top.sv
-core/primitives/scr1_reset_cells.sv
-core/primitives/scr1_cg.sv
-core/scr1_clk_ctrl.sv
-core/scr1_tapc_shift_reg.sv
-core/scr1_tapc.sv
-core/scr1_tapc_synchronizer.sv
-core/scr1_core_top.sv
-core/scr1_dm.sv
-core/scr1_dmi.sv
-core/scr1_scu.sv
diff --git a/verilog/rtl/syntacore_scr1/src/run_modemsim b/verilog/rtl/syntacore_scr1/src/run_modemsim
deleted file mode 100755
index ae5f764..0000000
--- a/verilog/rtl/syntacore_scr1/src/run_modemsim
+++ /dev/null
@@ -1,2 +0,0 @@
-vlib work
-vlog -f wb_top.files -f core.files +incdir+includes -sv
diff --git a/verilog/rtl/syntacore_scr1/src/wb_top.files b/verilog/rtl/syntacore_scr1/src/wb_top.files
deleted file mode 100644
index 87dd341..0000000
--- a/verilog/rtl/syntacore_scr1/src/wb_top.files
+++ /dev/null
@@ -1,9 +0,0 @@
-top/scr1_dmem_router.sv
-top/scr1_imem_router.sv
-top/scr1_dp_memory.sv
-top/scr1_tcm.sv
-top/scr1_timer.sv
-top/scr1_dmem_wb.sv
-top/scr1_imem_wb.sv
-top/scr1_top_wb.sv
-../../lib/sync_fifo.sv