)]}'
{
  "commit": "ef957a670b1b4689d09bf3ac1feef451ed011a43",
  "tree": "0d14161891ed6c9fa97a943d750f497c1f209217",
  "parents": [
    "9ae1f07e805bb992c90101470b9efda33de1018c"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Fri Apr 23 15:53:57 2021 -0400"
  },
  "committer": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Fri Apr 23 15:53:57 2021 -0400"
  },
  "message": "Updated the documentation to reflect the changes made to the source\ncode and the behavior of the logic analyzer.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "94286b8ac7337c596fcd361343ed1744baca2051",
      "old_mode": 33188,
      "old_path": "verilog/dv/README.md",
      "new_id": "1a834f733f4c819f00f611ce8a7338b3f8a2bace",
      "new_mode": 33188,
      "new_path": "verilog/dv/README.md"
    }
  ]
}