iverilog -g2005-sv -DFUNCTIONAL -DSIM -I /home/dinesha/workarea/efabless/MPW-3/pdk/sky130A \
-I /home/dinesha/workarea/opencore/git/riscduino/caravel/verilog/dv/caravel  \
-I /home/dinesha/workarea/opencore/git/riscduino/caravel/verilog/rtl \
-I ../../rtl/mbist/include \
-I ../    -I ../../../verilog/rtl \
wb_port_tb.v -o wb_port.vvp