OpenROAD 1 fb8ae93b6c7a5eb0e6fac83360a8a48d76c41885
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: /openLANE_flow/designs/axmul/runs/run1/tmp/merged_unpadded.lef
[WARNING ODB-0220] WARNING (LEFPARS-2036): SOURCE statement is obsolete in version 5.6 and later.
The LEF parser will ignore this statement.
To avoid this warning in the future, remove this statement from the LEF file with version 5.6 or later. See file /openLANE_flow/designs/axmul/runs/run1/tmp/merged_unpadded.lef at line 68110.

[INFO ODB-0223]     Created 13 technology layers
[INFO ODB-0224]     Created 25 technology vias
[INFO ODB-0225]     Created 441 library cells
[INFO ODB-0226] Finished LEF file:  /openLANE_flow/designs/axmul/runs/run1/tmp/merged_unpadded.lef
[INFO ODB-0127] Reading DEF file: /openLANE_flow/designs/axmul/runs/run1/tmp/routing/92-addspacers.obs.obs.def
[INFO ODB-0128] Design: axmul
[INFO ODB-0130]     Created 34 pins.
[INFO ODB-0131]     Created 51696 components and 193024 component-terminals.
[INFO ODB-0132]     Created 2 special nets and 192232 connections.
[INFO ODB-0133]     Created 226 nets and 792 connections.
[INFO ODB-0134] Finished DEF file: /openLANE_flow/designs/axmul/runs/run1/tmp/routing/92-addspacers.obs.obs.def
[INFO GRT-0020] Min routing layer: li1
[INFO GRT-0021] Max routing layer: met4
[INFO GRT-0022] Global adjustment: 0%
[INFO GRT-0023] Grid origin: (0, 0)
[WARNING GRT-0043] No OR_DEFAULT vias defined.
[INFO GRT-0224] Chose via L1M1_PR as default.
[INFO GRT-0224] Chose via M1M2_PR as default.
[INFO GRT-0224] Chose via M2M3_PR as default.
[INFO GRT-0224] Chose via M3M4_PR as default.
[INFO GRT-0224] Chose via M4M5_PR as default.
[INFO GRT-0088] Layer li1     Track-Pitch = 0.4600  line-2-Via Pitch: 0.3400
[INFO GRT-0088] Layer met1    Track-Pitch = 0.3400  line-2-Via Pitch: 0.3400
[INFO GRT-0088] Layer met2    Track-Pitch = 0.4600  line-2-Via Pitch: 0.3500
[INFO GRT-0088] Layer met3    Track-Pitch = 0.6800  line-2-Via Pitch: 0.6150
[INFO GRT-0088] Layer met4    Track-Pitch = 0.9200  line-2-Via Pitch: 0.6150
[INFO GRT-0003] Macros: 0
[INFO GRT-0004] Blockages: 268736
[INFO GRT-0019] Found 0 clock nets.
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 9
[INFO GRT-0017] Processing 270320 blockages on layer li1.
[INFO GRT-0017] Processing 103650 blockages on layer met1.
[INFO GRT-0017] Processing 12 blockages on layer met4.

[INFO GRT-0053] Routing resources analysis:
          Routing      Original      Derated      Resource
Layer     Direction    Resources     Resources    Reduction (%)
---------------------------------------------------------------
li1        Vertical       167700          1220          99.27%
met1       Horizontal     223600        143964          35.62%
met2       Vertical       167700        166175          0.91%
met3       Horizontal     111800        111972          -0.15%
met4       Vertical        78260         76597          2.12%
---------------------------------------------------------------

[INFO GRT-0191] Wirelength: 3195, Wirelength1: 0
[INFO GRT-0192] Number of segments: 488
[INFO GRT-0193] Number of shifts: 0
[INFO GRT-0097] First L Route.
[INFO GRT-0191] Wirelength: 3195, Wirelength1: 3195
[INFO GRT-0192] Number of segments: 488
[INFO GRT-0193] Number of shifts: 0
[INFO GRT-0135] Overflow report.
[INFO GRT-0136] Total hCap               : 255936
[INFO GRT-0137] Total vCap               : 243992
[INFO GRT-0138] Total usage              : 3195
[INFO GRT-0139] Max H overflow           : 0
[INFO GRT-0140] Max V overflow           : 0
[INFO GRT-0141] Max overflow             : 0
[INFO GRT-0142] Number of overflow edges : 0
[INFO GRT-0143] H   overflow             : 0
[INFO GRT-0144] V   overflow             : 0
[INFO GRT-0145] Final overflow           : 0

[INFO GRT-0098] Second L Route.
[INFO GRT-0135] Overflow report.
[INFO GRT-0136] Total hCap               : 255936
[INFO GRT-0137] Total vCap               : 243992
[INFO GRT-0138] Total usage              : 3195
[INFO GRT-0139] Max H overflow           : 0
[INFO GRT-0140] Max V overflow           : 0
[INFO GRT-0141] Max overflow             : 0
[INFO GRT-0142] Number of overflow edges : 0
[INFO GRT-0143] H   overflow             : 0
[INFO GRT-0144] V   overflow             : 0
[INFO GRT-0145] Final overflow           : 0

[INFO GRT-0099] First Z Route.
[INFO GRT-0135] Overflow report.
[INFO GRT-0136] Total hCap               : 255936
[INFO GRT-0137] Total vCap               : 243992
[INFO GRT-0138] Total usage              : 3195
[INFO GRT-0139] Max H overflow           : 0
[INFO GRT-0140] Max V overflow           : 0
[INFO GRT-0141] Max overflow             : 0
[INFO GRT-0142] Number of overflow edges : 0
[INFO GRT-0143] H   overflow             : 0
[INFO GRT-0144] V   overflow             : 0
[INFO GRT-0145] Final overflow           : 0

[INFO GRT-0100] LV routing round 0, enlarge 10.
[INFO GRT-0182] 10 threshold, 10 expand.
[INFO GRT-0126] Overflow report:
[INFO GRT-0127] Total usage          : 3195
[INFO GRT-0128] Max H overflow       : 0
[INFO GRT-0129] Max V overflow       : 0
[INFO GRT-0130] Max overflow         : 0
[INFO GRT-0131] Number overflow edges: 0
[INFO GRT-0132] H   overflow         : 0
[INFO GRT-0133] V   overflow         : 0
[INFO GRT-0134] Final overflow       : 0

[INFO GRT-0100] LV routing round 1, enlarge 15.
[INFO GRT-0182] 5 threshold, 15 expand.
[INFO GRT-0126] Overflow report:
[INFO GRT-0127] Total usage          : 3195
[INFO GRT-0128] Max H overflow       : 0
[INFO GRT-0129] Max V overflow       : 0
[INFO GRT-0130] Max overflow         : 0
[INFO GRT-0131] Number overflow edges: 0
[INFO GRT-0132] H   overflow         : 0
[INFO GRT-0133] V   overflow         : 0
[INFO GRT-0134] Final overflow       : 0

[INFO GRT-0100] LV routing round 2, enlarge 20.
[INFO GRT-0182] 1 threshold, 20 expand.
[INFO GRT-0126] Overflow report:
[INFO GRT-0127] Total usage          : 3195
[INFO GRT-0128] Max H overflow       : 0
[INFO GRT-0129] Max V overflow       : 0
[INFO GRT-0130] Max overflow         : 0
[INFO GRT-0131] Number overflow edges: 0
[INFO GRT-0132] H   overflow         : 0
[INFO GRT-0133] V   overflow         : 0
[INFO GRT-0134] Final overflow       : 0

Usage checked
[INFO GRT-0105] Maze routing finished.
Final 2D results:
[INFO GRT-0126] Overflow report:
[INFO GRT-0127] Total usage          : 3195
[INFO GRT-0128] Max H overflow       : 0
[INFO GRT-0129] Max V overflow       : 0
[INFO GRT-0130] Max overflow         : 0
[INFO GRT-0131] Number overflow edges: 0
[INFO GRT-0132] H   overflow         : 0
[INFO GRT-0133] V   overflow         : 0
[INFO GRT-0134] Final overflow       : 0

[INFO GRT-0106] Layer assignment begins.
[INFO GRT-0107] Layer assignment finished.
[INFO GRT-0108] Post-processing begins.
[INFO GRT-0109] Post-processing finished.
 Starting via filling.
[INFO GRT-0197] Via related to pin nodes: 1075
[INFO GRT-0198] Via related Steiner nodes: 49
[INFO GRT-0199] Via filling finished.
[INFO GRT-0111] Final number of vias: 1293
[INFO GRT-0112] Final usage 3D: 7048
[WARNING GRT-0211] dbGcellGrid already exists in db. Clearing existing dbGCellGrid.

[INFO GRT-0096] Final congestion report:
Layer         Resource        Demand        Usage (%)    Max H / Max V / Total Overflow
---------------------------------------------------------------------------------------
li1               1220             5            0.41%             0 /  0 /  0
met1            143964          1722            1.20%             0 /  0 /  0
met2            166175          1409            0.85%             0 /  0 /  0
met3            111972            33            0.03%             0 /  0 /  0
met4             76597             0            0.00%             0 /  0 /  0
---------------------------------------------------------------------------------------
Total           499928          3169            0.63%             0 /  0 /  0

[INFO GRT-0018] Total wirelength: 27324 um
[INFO GRT-0014] Routed nets: 226
INFO:Skipped CTS Stage so reading base SDC file
create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
puts "\[INFO\]: Setting output delay to: $output_delay_value"
[INFO]: Setting output delay to: 2.0
puts "\[INFO\]: Setting input delay to: $input_delay_value"
[INFO]: Setting input delay to: 2.0
set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
set all_inputs_wo_clk_rst $all_inputs_wo_clk
# correct resetn
set_input_delay $input_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
#set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
set_output_delay $output_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
[INFO]: Setting load to: 0.01765
set_load  $cap_load [all_outputs]
check_report
No paths found.
check_report_end
timing_report
No paths found.
timing_report_end
min_max_report
No paths found.
min_max_report_end
wns_report
wns 0.00
wns_report_end
tns_report
tns 0.00
tns_report_end