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      "message": "WIP digitalcore macro. Doesn\u0027t harden yet\n"
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      "message": "Add WIP dtop and ring controller\n"
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      "message": "Add collapsering_macro. Hardens okay.\n\nDoesn\u0027t \"meet\" timing, but there really isn\u0027t any timing to meet here\nexcept in the FF clock dividers which are suspicious and best effort\nanyways.\n"
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      "message": "Fix schematic clkmux bus for verilog netlist\n"
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        "time": "Sun Oct 17 12:39:16 2021 -0700"
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      "message": "14 stage collapsing ring\n"
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      "message": "Fix floating trim signals\n"
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      "message": "Add WIP collapsing ring osc\n"
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