)]}'
{
  "commit": "c170f923f97375ee6c3814b6722fdf33b665a32a",
  "tree": "226460b2197e965c7997c0dd4886ab832e894ec1",
  "parents": [
    "250d0f5431b053fe17a3f8eebe56fdd1dee9050c"
  ],
  "author": {
    "name": "Harrison Pham",
    "email": "harrison@harrisonpham.com",
    "time": "Sat Oct 23 16:01:20 2021 -0700"
  },
  "committer": {
    "name": "Harrison Pham",
    "email": "harrison@harrisonpham.com",
    "time": "Sat Oct 23 16:01:20 2021 -0700"
  },
  "message": "Digital core and ring macros harden properly.\n\nCorrectly supports multiple clock domains.\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "077ea1dbf7e613fc1a9f29467f1428fd0fdab18f",
      "new_mode": 33188,
      "new_path": "envsetup"
    },
    {
      "type": "modify",
      "old_id": "6da1ce44617272fd980f67f99cd17bf3d928e026",
      "old_mode": 33188,
      "old_path": "ip/randsack/rtl/collapsering_macro.v",
      "new_id": "fd17492fca29b7a1d329538008fa92b0bd97ae4b",
      "new_mode": 33188,
      "new_path": "ip/randsack/rtl/collapsering_macro.v"
    },
    {
      "type": "rename",
      "old_id": "86e4b5b4f5803612d7a043f69f743856722b231b",
      "old_mode": 33188,
      "old_path": "ip/randsack/rtl/dtop.v",
      "new_id": "9c41fb7ed9f6ecd24f24b6f9c3e3d95239d657c0",
      "new_mode": 33188,
      "new_path": "ip/randsack/rtl/digitalcore_macro.v",
      "score": 88
    },
    {
      "type": "modify",
      "old_id": "002b918c47019256b8ffb0cab8b160a853fa7d84",
      "old_mode": 33188,
      "old_path": "ip/randsack/rtl/ring_control.v",
      "new_id": "5efe22225ca4f18e8b0b4ab64898b85db559077e",
      "new_mode": 33188,
      "new_path": "ip/randsack/rtl/ring_control.v"
    },
    {
      "type": "rename",
      "old_id": "4fe9f0c1899636d97155ed75a3e0973bf91b66c2",
      "old_mode": 33188,
      "old_path": "ip/third_party/picorv32_wb/simpleuart.v",
      "new_id": "9e5d66f95bd4844834d05902ee053a496dd0b41e",
      "new_mode": 33188,
      "new_path": "ip/third_party/picorv32_wb/simpleuart_div16_wb.v",
      "score": 94
    },
    {
      "type": "modify",
      "old_id": "28171c80a4699c08a1623f8476eb459921187878",
      "old_mode": 33188,
      "old_path": "openlane/digitalcore_macro/base.sdc",
      "new_id": "5efe1310c821c423804756d38175017f83b8640b",
      "new_mode": 33188,
      "new_path": "openlane/digitalcore_macro/base.sdc"
    },
    {
      "type": "modify",
      "old_id": "8f6a898706fce2276abff5bd06df4252e7c17891",
      "old_mode": 33261,
      "old_path": "openlane/digitalcore_macro/config.tcl",
      "new_id": "76c41aa1b591ce79609eaba71599d6b878cd6d44",
      "new_mode": 33261,
      "new_path": "openlane/digitalcore_macro/config.tcl"
    },
    {
      "type": "modify",
      "old_id": "2fda806ab62cbe43d3a6b2844e4bab975333e67b",
      "old_mode": 33188,
      "old_path": "openlane/digitalcore_macro/pin_order.cfg",
      "new_id": "14412b6a635305a016f198bfc3d0c9fdc1b8cfa0",
      "new_mode": 33188,
      "new_path": "openlane/digitalcore_macro/pin_order.cfg"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "2eb97506d2faa3f9c2923bd8a1f9d0cfddb55894",
      "new_mode": 33188,
      "new_path": "verilog/dv/randsack_netlists.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "07e13f7fbecb234024949c43f86a7761bb71eb46",
      "new_mode": 33188,
      "new_path": "verilog/dv/randsack_regrw_directed/Makefile"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "2218b985b0da7b2e67bb57e36067c2b72d9dad9e",
      "new_mode": 33188,
      "new_path": "verilog/dv/randsack_regrw_directed/randsack_regrw_directed.c"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "ef24cb66bed7eb942e08a477e0156b6ee84acf82",
      "new_mode": 33188,
      "new_path": "verilog/dv/randsack_regrw_directed/randsack_regrw_directed_tb.v"
    },
    {
      "type": "modify",
      "old_id": "5ee1ceecfb5f08335c33a73de2e09ef869af17a9",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project_wrapper.v",
      "new_id": "646c96de48050c7fdf098aa3fb747a5d68a8933d",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_project_wrapper.v"
    }
  ]
}
