blob: 4fe0a87e96d6f2da4117c32b562fcf632bd627ab [file] [log] [blame]
// SPDX-FileCopyrightText:
// 2020 Efabless Corporation
// 2021 Matt Venn
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// SPDX-License-Identifier: Apache-2.0
// Include caravel global defines for the number of the user project IO pads
`include "defines.v"
`define USE_POWER_PINS
`ifdef GL
// Assume default net type to be wire because GL netlists don't have the wire definitions
`default_nettype wire
`include "gl/user_project_wrapper.v"
`include "gl/wrapped_wb_openram_shim.lvs.powered.v"
`else
`include "user_project_wrapper.v"
// 10 wb_openram_shim : /home/matt/work/asic-workshop/shuttle3-mpw-3/openlane/designs/wrapped_wb_openram_shim
`include "wrapped_wb_openram_shim/wrapper.v"
`include "wrapped_wb_openram_shim/wb_openram_wrapper/src/wb_openram_wrapper.v"
// include openram model
`include "libs.ref/sky130_sram_macros/verilog/sky130_sram_1kbyte_1rw1r_32x256_8.v"
`endif