diff --git a/.gitmodules b/.gitmodules
index e020a55..75fcba6 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -4,3 +4,6 @@
 [submodule "wb_openram_wrapper"]
 	path = wb_openram_wrapper
 	url = https://github.com/embelon/wb_openram_wrapper
+[submodule "wb_ram_bus_mux"]
+	path = wb_ram_bus_mux
+	url = https://github.com/embelon/wb_ram_bus_mux.git
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index e6ba02c..1e90b84 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -39,9 +39,9 @@
 
 ## Clock configurations
 set ::env(CLOCK_PORT) [list {wb_clk_i user_clock2}]
-set ::env(CLOCK_NET) [list {openram_1kB.openram_clk0 wb_openram_wrapper.wb_clk_i}]
+set ::env(CLOCK_NET) [list {openram_1kB.openram_clk0 wb_openram_wrapper.wb_clk_i wb_bus_mux.wb_clk_i}]
 
-set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PERIOD) "13"
 
 ## Internal Macros
 ### Macro PDN Connections
@@ -51,7 +51,8 @@
 
 set ::env(FP_PDN_MACRO_HOOKS) "\
 	wb_openram_wrapper vccd1 vssd1 \
-	openram_1kB vccd1 vssd1 "
+	openram_1kB vccd1 vssd1 \
+	wb_bus_mux vccd1 vssd1 "
 
 set ::env(VDD_NETS) "vccd1 vccd2 vdda1 vdda2"
 set ::env(GND_NETS) "vssd1 vssd2 vssa1 vssa2"
@@ -71,14 +72,17 @@
 set ::env(VERILOG_FILES_BLACKBOX) "\
 	$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
 	$script_dir/../../wb_openram_wrapper/src/wb_openram_wrapper.v \
+	$script_dir/../../wb_ram_bus_mux/src/wb_ram_bus_mux.v \
 	$::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_sram_macros/verilog/sky130_sram_1kbyte_1rw1r_32x256_8.v"
 
 set ::env(EXTRA_LEFS) "\
 	$script_dir/../../wb_openram_wrapper/lef/wb_openram_wrapper.lef \
+	$script_dir/../../wb_ram_bus_mux/lef/wb_ram_bus_mux.lef \
 	$::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_sram_macros/lef/sky130_sram_1kbyte_1rw1r_32x256_8.lef"
 
 set ::env(EXTRA_GDS_FILES) "\
 	$script_dir/../../wb_openram_wrapper/gds/wb_openram_wrapper.gds \
+	$script_dir/../../wb_ram_bus_mux/gds/wb_ram_bus_mux.gds \
 	$::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_sram_macros/gds/sky130_sram_1kbyte_1rw1r_32x256_8.gds"
 
 # use 4 cores
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index a01708d..82b26d0 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1,2 +1,3 @@
 openram_1kB 1000 1000 N
-wb_openram_wrapper 2000 1000 N
+wb_openram_wrapper 1700 700 N
+wb_bus_mux 2000 600 N
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 1e7da3a..fb6fd06 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -22,9 +22,11 @@
     `default_nettype wire
     `include "gl/user_project_wrapper.v"
     `include "../wb_openram_wrapper/src/wb_openram_wrapper.v"
+    `include "../wb_ram_bus_mux/src/wb_ram_bus_mux.v"
     `include "libs.ref/sky130_sram_macros/verilog/sky130_sram_1kbyte_1rw1r_32x256_8.v"
 `else
     `include "user_project_wrapper.v"
     `include "../../wb_openram_wrapper/src/wb_openram_wrapper.v"
+    `include "../../wb_ram_bus_mux/src/wb_ram_bus_mux.v"
     `include "libs.ref/sky130_sram_macros/verilog/sky130_sram_1kbyte_1rw1r_32x256_8.v"
 `endif
\ No newline at end of file
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 7c2ad82..7418f42 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -82,6 +82,7 @@
 /* User project is instantiated  here   */
 /*--------------------------------------*/
 
+// Signals connecting OpenRAM with its wrapper
 wire openram_clk0;
 wire openram_csb0;
 wire openram_web0;
@@ -90,6 +91,16 @@
 wire [31:0] openram_din0;
 wire [31:0] openram_dout0;
 
+// Signals connecting OpenRAM wrapper to Bus MUX
+wire wbs_or_stb;
+wire wbs_or_cyc;
+wire wbs_or_we;
+wire [3:0] wbs_or_sel;
+wire [31:0] wbs_or_dat_i;
+wire wbs_or_ack;
+wire [31:0] wbs_or_dat_o;
+
+
 sky130_sram_1kbyte_1rw1r_32x256_8 openram_1kB
 (
 `ifdef USE_POWER_PINS
@@ -111,29 +122,68 @@
 `ifdef USE_POWER_PINS
     .vccd1 (vccd1),	    // User area 1 1.8V supply
     .vssd1 (vssd1),	    // User area 1 digital ground
- `endif
+`endif
 
     // Wishbone port A
-    .wb_clk_i (wb_clk_i),
-    .wb_rst_i (wb_rst_i),
-    .wbs_stb_i (wbs_stb_i),
-    .wbs_cyc_i (wbs_cyc_i),
-    .wbs_we_i (wbs_we_i),
-    .wbs_sel_i (wbs_sel_i),
-    .wbs_dat_i (wbs_dat_i),
-    .wbs_adr_i (wbs_adr_i),
-    .wbs_ack_o (wbs_ack_o),
-    .wbs_dat_o (wbs_dat_o),
+    .wb_clk_i       (wb_clk_i),
+    .wb_rst_i       (wb_rst_i),
+    .wbs_stb_i      (wbs_or_stb),
+    .wbs_cyc_i      (wbs_or_cyc),
+    .wbs_we_i       (wbs_or_we),
+    .wbs_sel_i      (wbs_or_sel),
+    .wbs_dat_i      (wbs_or_dat_o),
+    .wbs_adr_i      (wbs_adr_i),
+    .wbs_ack_o      (wbs_or_ack),
+    .wbs_dat_o      (wbs_or_dat_i),
 
     // OpenRAM interface
     // Port 0: RW
-    .ram_clk0 (openram_clk0),       // clock
-    .ram_csb0 (openram_csb0),       // active low chip select
-    .ram_web0 (openram_web0),       // active low write control
-    .ram_wmask0 (openram_wmask0),   // write mask
-    .ram_addr0 (openram_addr0),
-    .ram_din0 (openram_dout0),
-    .ram_dout0 (openram_din0)
+    .ram_clk0       (openram_clk0),         // clock
+    .ram_csb0       (openram_csb0),         // active low chip select
+    .ram_web0       (openram_web0),         // active low write control
+    .ram_wmask0     (openram_wmask0),       // write mask
+    .ram_addr0      (openram_addr0),
+    .ram_din0       (openram_dout0),
+    .ram_dout0      (openram_din0)
+);
+
+wb_ram_bus_mux wb_bus_mux
+(
+`ifdef USE_POWER_PINS
+    .vccd1 (vccd1),	    // User area 1 1.8V supply
+    .vssd1 (vssd1),	    // User area 1 digital ground
+`endif
+
+    // Wishbone UFP (Upward Facing Port)
+    .wb_clk_i        (wb_clk_i),
+    .wb_rst_i        (wb_rst_i),
+    .wbs_ufp_stb_i   (wbs_stb_i),
+    .wbs_ufp_cyc_i   (wbs_cyc_i),
+    .wbs_ufp_we_i    (wbs_we_i),
+    .wbs_ufp_sel_i   (wbs_sel_i),
+    .wbs_ufp_dat_i   (wbs_dat_i),
+    .wbs_ufp_adr_i   (wbs_adr_i),
+    .wbs_ufp_ack_o   (wbs_ack_o), 
+    .wbs_ufp_dat_o   (wbs_dat_o),
+/*
+    // Wishbone HR (Downward Facing Port) - HyperRAM driver
+    output          wbs_hr_stb_o,
+    output          wbs_hr_cyc_o,
+    output          wbs_hr_we_o,
+    output  [3:0]   wbs_hr_sel_o,
+    input   [31:0]  wbs_hr_dat_i,
+    input           wbs_hr_ack_i,
+    output  [31:0]  wbs_hr_dat_o,
+*/
+
+    // Wishbone OR (Downward Facing Port) - OpenRAM
+    .wbs_or_stb_o    (wbs_or_stb),
+    .wbs_or_cyc_o    (wbs_or_cyc),
+    .wbs_or_we_o     (wbs_or_we),
+    .wbs_or_sel_o    (wbs_or_sel),
+    .wbs_or_dat_i    (wbs_or_dat_i),
+    .wbs_or_ack_i    (wbs_or_ack),
+    .wbs_or_dat_o    (wbs_or_dat_o)
 );
 
 endmodule	// user_project_wrapper
diff --git a/wb_ram_bus_mux b/wb_ram_bus_mux
new file mode 160000
index 0000000..0d83a09
--- /dev/null
+++ b/wb_ram_bus_mux
@@ -0,0 +1 @@
+Subproject commit 0d83a09ad81e792d6d6f05d926ec2c1d6abfc2f9