diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 0154db3..c41fc64 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -138,8 +138,8 @@
     .web0 (openram_web0),       // active low write control
     .wmask0 (openram_wmask0),   // write mask
     .addr0 (openram_addr0),
-    .din0 (openram_din0),
-    .dout0 (openram_dout0)
+    .din0 (openram_dout0),
+    .dout0 (openram_din0)
 );
 
 endmodule	// user_project_wrapper