)]}'
{
  "commit": "9e314b9ee3de1b0feb510430b969385ebff7ec21",
  "tree": "441fdcb8ceefca9b562cb6bc8aa96a7f269ced70",
  "parents": [
    "af9dbfc2c5dfc5b94da72f89eee773c01f641f0d"
  ],
  "author": {
    "name": "embelon",
    "email": "78412338+embelon@users.noreply.github.com",
    "time": "Thu Nov 25 21:23:21 2021 +0100"
  },
  "committer": {
    "name": "embelon",
    "email": "78412338+embelon@users.noreply.github.com",
    "time": "Thu Nov 25 21:23:21 2021 +0100"
  },
  "message": "Fixed unaligned access over Wishbone bus that results in picorv32 hang. Improved readability.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "589f1fecb8a69ff86eeed2a8ae88b1a27150f729",
      "old_mode": 33188,
      "old_path": "verilog/dv/wb_openram/wb_openram.c",
      "new_id": "090a44de8e67c3d3a1ce59275995450c47e05a12",
      "new_mode": 33188,
      "new_path": "verilog/dv/wb_openram/wb_openram.c"
    }
  ]
}