)]}'
{
  "commit": "58d0b6de768e7bd7dd0c464aab0fae873789c800",
  "tree": "b4c55dcc41355b1f5068c46017599f7afe41ddad",
  "parents": [
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  "author": {
    "name": "embelon",
    "email": "78412338+embelon@users.noreply.github.com",
    "time": "Thu Oct 14 20:14:18 2021 +0200"
  },
  "committer": {
    "name": "embelon",
    "email": "78412338+embelon@users.noreply.github.com",
    "time": "Thu Oct 14 20:14:18 2021 +0200"
  },
  "message": "Added openram_testchip as a submodule to use verilog blackbox, gds and lef.\n",
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