diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index b159322..9012d2b 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -157,9 +157,9 @@
 );
 
 
-wire hb_dq_oen;
+// wire hb_dq_oen;
 
-wb_hyperram hyperram 
+wb_hyperram wb_hyperram 
 (
 `ifdef USE_POWER_PINS
     .vccd1 (vccd1),	    // User area 1 1.8V supply
@@ -188,11 +188,11 @@
     .hb_rwds_oen    (io_oeb[12]),
     .hb_rwds_i      (io_in[12]),        
     .hb_dq_o        (io_out[20:13]),
-    .hb_dq_oen      (hb_dq_oen),
+    .hb_dq_oen      (io_oeb[20:13]),
     .hb_dq_i        (io_in[20:13])
 );
 
-assign io_oeb[20:13] = {8{hb_dq_oen}};
+//assign io_oeb[20:13] = {8{hb_dq_oen}};
 
 // enable outputs for rst, csn, clk, clkn 
 assign io_oeb[11:8] = 4'h0;
diff --git a/wb_hyperram b/wb_hyperram
index 3f7b51f..0f613d4 160000
--- a/wb_hyperram
+++ b/wb_hyperram
@@ -1 +1 @@
-Subproject commit 3f7b51fd6d8a2a68ff8115949e1d3fde66f333f2
+Subproject commit 0f613d4c5f079ca8a0be4f4fb82946b26c943c7c