| /root/1v8_ldo_design_in_skywaters_130nm/Makefile |
| /root/1v8_ldo_design_in_skywaters_130nm/docs/environment.yml |
| /root/1v8_ldo_design_in_skywaters_130nm/docs/Makefile |
| /root/1v8_ldo_design_in_skywaters_130nm/docs/source/index.rst |
| /root/1v8_ldo_design_in_skywaters_130nm/docs/source/conf.py |
| /root/1v8_ldo_design_in_skywaters_130nm/verilog/dv/Makefile |
| /root/1v8_ldo_design_in_skywaters_130nm/verilog/dv/mprj_por/mprj_por_tb.v |
| /root/1v8_ldo_design_in_skywaters_130nm/verilog/dv/mprj_por/Makefile |
| /root/1v8_ldo_design_in_skywaters_130nm/verilog/dv/mprj_por/mprj_por.c |
| /root/1v8_ldo_design_in_skywaters_130nm/verilog/rtl/example_por.v |
| /root/1v8_ldo_design_in_skywaters_130nm/verilog/rtl/uprj_analog_netlists.v |
| /root/1v8_ldo_design_in_skywaters_130nm/verilog/rtl/user_analog_proj_example.v |
| /root/1v8_ldo_design_in_skywaters_130nm/verilog/rtl/user_analog_project_wrapper.v |
| /root/1v8_ldo_design_in_skywaters_130nm/scripts/run_standard_lvs.py |
| /root/1v8_ldo_design_in_skywaters_130nm/xschem/xschemrc |
| /root/1v8_ldo_design_in_skywaters_130nm/xschem/example_por.sch |
| /root/1v8_ldo_design_in_skywaters_130nm/xschem/op_point_test |
| /root/1v8_ldo_design_in_skywaters_130nm/xschem/example_por.sym |
| /root/1v8_ldo_design_in_skywaters_130nm/xschem/example_por_tb.spice.orig |
| /root/1v8_ldo_design_in_skywaters_130nm/xschem/user_analog_project_wrapper.sym |
| /root/1v8_ldo_design_in_skywaters_130nm/xschem/example_por_tb.sch |
| /root/1v8_ldo_design_in_skywaters_130nm/xschem/user_analog_project_wrapper.sch |
| /root/1v8_ldo_design_in_skywaters_130nm/xschem/analog_wrapper_tb.sch |
| /root/1v8_ldo_design_in_skywaters_130nm/xschem/.spiceinit |
| /root/1v8_ldo_design_in_skywaters_130nm/xschem/ldo_v1/bgr_sym.sym |
| /root/1v8_ldo_design_in_skywaters_130nm/xschem/ldo_v1/ldo_v1_sim.sch |
| /root/1v8_ldo_design_in_skywaters_130nm/xschem/ldo_v1/Error_Amp.sch |
| /root/1v8_ldo_design_in_skywaters_130nm/xschem/ldo_v1/Error_Amp.sym |
| /root/1v8_ldo_design_in_skywaters_130nm/xschem/ldo_v1/bgr_sym.sch |
| /root/1v8_ldo_design_in_skywaters_130nm/xschem/ldo_v1/ldo_v1_lvs.sch |
| /root/1v8_ldo_design_in_skywaters_130nm/xschem/ldo_v2/ldo_v2_lvs.sch |
| /root/1v8_ldo_design_in_skywaters_130nm/xschem/ldo_v2/Error_Amp.sch |
| /root/1v8_ldo_design_in_skywaters_130nm/xschem/ldo_v2/ldo_v2.sch |
| /root/1v8_ldo_design_in_skywaters_130nm/xschem/ldo_v2/bgr2.sym |
| /root/1v8_ldo_design_in_skywaters_130nm/xschem/ldo_v2/Error_Amp.sym |
| /root/1v8_ldo_design_in_skywaters_130nm/xschem/ldo_v2/ldo_v2_sim.sch |
| /root/1v8_ldo_design_in_skywaters_130nm/xschem/ldo_v2/bgr2.sch |
| /root/1v8_ldo_design_in_skywaters_130nm/gds/ldo_v1/ldo_v1_extracted.spi |
| /root/1v8_ldo_design_in_skywaters_130nm/openlane/Makefile |
| /root/1v8_ldo_design_in_skywaters_130nm/netgen/run_lvs_wrapper_verilog.sh |
| /root/1v8_ldo_design_in_skywaters_130nm/netgen/run_lvs_por.sh |
| /root/1v8_ldo_design_in_skywaters_130nm/netgen/run_lvs_wrapper_xschem.sh |
