tree ac34c32719e92a95375578a447b5324b10c11f4d
parent 3dc29b1a727082c620b308b4894b625acc803c92
author Tim Edwards <tim@opencircuitdesign.com> 1632840649 -0400
committer Tim Edwards <tim@opencircuitdesign.com> 1632840649 -0400

Modified the user_analog_project_wrapper layouts (empty and example)
to add the metal4 and metal5 layers on io_analog[6:4] that are part
of the top level layout.  This will show users where the layers are
so that they do not route close enough to create DRC violations where
they cannot see them.