/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/DFFRAM.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/DFFRAMBB.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/__uprj_analog_netlists.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/__uprj_netlists.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/__user_analog_project_wrapper.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/__user_project_wrapper.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/caravan.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/caravan_netlists.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/caravel.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/caravel_clocking.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/chip_io.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/chip_io_alt.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/clock_div.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/convert_gpio_sigs.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/counter_timer_high.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/counter_timer_low.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/digital_pll.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/digital_pll_controller.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/gpio_control_block.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/gpio_logic_high.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/gpio_wb.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/housekeeping_spi.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/la_wb.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/mem_wb.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/mgmt_core.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/mgmt_protect.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/mgmt_protect_hv.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/mgmt_soc.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/mprj2_logic_high.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/mprj_ctrl.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/mprj_io.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/mprj_logic_high.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/pads.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/picorv32.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/ring_osc2x13.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/simple_por.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/simple_spi_master.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/simpleuart.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/spimemio.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/sram_1rw1r_32_256_8_sky130.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/storage.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/storage_bridge_wb.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/sysctrl.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/verilog/rtl/wb_intercon.v: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/scripts/set_user_id.py: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/scripts/generate_fill.py: OK
/root/1v8_ldo_design_in_skywaters_130nm/caravel/scripts/compositor.py: OK