)]}' { "commit": "f3e51676cc7a06a2daa8d8b10213abe07a4ff6b0", "tree": "7e8433401fb9f473578874f75ba64a3a3616a104", "parents": [ "bee22b927b7e7c9c229f9aace599b6168de031dd" ], "author": { "name": "Philipp Gühring", "email": "pg@futureware.at", "time": "Sat Nov 13 17:11:10 2021 +0100" }, "committer": { "name": "Philipp Gühring", "email": "pg@futureware.at", "time": "Sat Nov 13 17:11:10 2021 +0100" }, "message": "Autogenerated updates\n", "tree_diff": [ { "type": "modify", "old_id": "09216337bb5ab2f2fe0fd260b8e41648b0e371d0", "old_mode": 33188, "old_path": "verilog/rtl/user_proj_cells.v", "new_id": "5d6009e7a3c763d254d07b7b305929c4254bdc66", "new_mode": 33188, "new_path": "verilog/rtl/user_proj_cells.v" }, { "type": "modify", "old_id": "5b92dd47f9c5f6c35d227be78fb93362696b13a9", "old_mode": 33188, "old_path": "verilog/rtl/user_proj_example.v", "new_id": "6d8ad45766f7220362a9b0ea2eac3816c563b745", "new_mode": 33188, "new_path": "verilog/rtl/user_proj_example.v" } ] }