diff --git a/verilog/rtl/user_proj_cells.v b/verilog/rtl/user_proj_cells.v
index 0921633..5d6009e 100644
--- a/verilog/rtl/user_proj_cells.v
+++ b/verilog/rtl/user_proj_cells.v
@@ -84,6 +84,16 @@
 );
 endmodule
 
+module CLKBUF2(
+  inout A, // input
+  inout Y, // output
+     `ifdef USE_POWER_PINS
+	inout VPWR, // cell power supply
+	inout VGND  // cell ground supply
+     `endif
+);
+endmodule
+
 module INV(
   inout A, // input
   inout Y, // output
@@ -169,6 +179,42 @@
 );
 endmodule
 
+module NOR2X1(
+  inout A, // input
+  inout B, // input
+  inout Y, // output
+     `ifdef USE_POWER_PINS
+	inout VPWR, // cell power supply
+	inout VGND  // cell ground supply
+     `endif
+);
+endmodule
+
+module OAI21X1(
+  inout A, // input
+  inout B, // input
+  inout C, // input
+  inout Y, // output
+     `ifdef USE_POWER_PINS
+	inout VPWR, // cell power supply
+	inout VGND  // cell ground supply
+     `endif
+);
+endmodule
+
+module OAI22X1(
+  inout A, // input
+  inout B, // input
+  inout C, // input
+  inout D, // input
+  inout Y, // output
+     `ifdef USE_POWER_PINS
+	inout VPWR, // cell power supply
+	inout VGND  // cell ground supply
+     `endif
+);
+endmodule
+
 module OR2X1(
   inout A, // input
   inout B, // input
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 5b92dd4..6d8ad45 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -11,7 +11,6 @@
     parameter BITS = 32
 )(
 `ifdef USE_POWER_PINS
-<<<<<<< HEAD
     inout vdda1,        // User area 1 3.3V supply
     inout vdda2,        // User area 2 3.3V supply
     inout vssa1,        // User area 1 analog ground
@@ -20,10 +19,6 @@
     inout vccd2,        // User area 2 1.8v supply
     inout vssd1,        // User area 1 digital ground
     inout vssd2,        // User area 2 digital ground
-=======
-    inout vccd1,	// User area 1 1.8V supply
-    inout vssd1,	// User area 1 digital ground
->>>>>>> c5da9e9885e361d05dee2aa6303a69fc26423c8e
 `endif
 
     // Wishbone Slave ports (WB MI A)
@@ -119,7 +114,7 @@
   .A(io_in[19]),
   .Y(io_out[20]),
 );
-INV INV(
+CLKBUF2 CLKBUF2(
  `ifdef USE_POWER_PINS
   .VPWR(vccd1),
   .VGND(vssd1),
@@ -127,7 +122,7 @@
   .A(io_in[21]),
   .Y(io_out[22]),
 );
-INVX1 INVX1(
+INV INV(
  `ifdef USE_POWER_PINS
   .VPWR(vccd1),
   .VGND(vssd1),
@@ -135,7 +130,7 @@
   .A(io_in[23]),
   .Y(io_out[24]),
 );
-INVX2 INVX2(
+INVX1 INVX1(
  `ifdef USE_POWER_PINS
   .VPWR(vccd1),
   .VGND(vssd1),
@@ -143,7 +138,7 @@
   .A(io_in[25]),
   .Y(io_out[26]),
 );
-INVX4 INVX4(
+INVX2 INVX2(
  `ifdef USE_POWER_PINS
   .VPWR(vccd1),
   .VGND(vssd1),
@@ -151,7 +146,7 @@
   .A(io_in[27]),
   .Y(io_out[28]),
 );
-INVX8 INVX8(
+INVX4 INVX4(
  `ifdef USE_POWER_PINS
   .VPWR(vccd1),
   .VGND(vssd1),
@@ -159,70 +154,108 @@
   .A(io_in[29]),
   .Y(io_out[30]),
 );
-MUX2X1 MUX2X1(
+INVX8 INVX8(
  `ifdef USE_POWER_PINS
   .VPWR(vccd1),
   .VGND(vssd1),
  `endif
   .A(io_in[31]),
-  .B(io_in[32]),
-  .S(io_in[33]),
-  .Y(io_out[34]),
+  .Y(io_out[32]),
+);
+MUX2X1 MUX2X1(
+ `ifdef USE_POWER_PINS
+  .VPWR(vccd1),
+  .VGND(vssd1),
+ `endif
+  .A(io_in[33]),
+  .B(io_in[34]),
+  .S(io_in[35]),
+  .Y(io_out[36]),
 );
 NAND2X1 NAND2X1(
  `ifdef USE_POWER_PINS
   .VPWR(vccd1),
   .VGND(vssd1),
  `endif
-  .A(io_in[35]),
-  .B(io_in[36]),
-  .Y(io_out[37]),
+  .A(io_in[37]),
+  .B(la_data_in[0]),
+  .Y(la_data_out[1]),
 );
 NAND3X1 NAND3X1(
  `ifdef USE_POWER_PINS
   .VPWR(vccd1),
   .VGND(vssd1),
  `endif
-  .A(la_data_in[0]),
-  .B(la_data_in[1]),
-  .C(la_data_in[2]),
-  .Y(la_data_out[3]),
+  .A(la_data_in[2]),
+  .B(la_data_in[3]),
+  .C(la_data_in[4]),
+  .Y(la_data_out[5]),
 );
-OR2X1 OR2X1(
+NOR2X1 NOR2X1(
  `ifdef USE_POWER_PINS
   .VPWR(vccd1),
   .VGND(vssd1),
  `endif
-  .A(la_data_in[4]),
-  .B(la_data_in[5]),
-  .Y(la_data_out[6]),
+  .A(la_data_in[6]),
+  .B(la_data_in[7]),
+  .Y(la_data_out[8]),
 );
-OR2X2 OR2X2(
+OAI21X1 OAI21X1(
  `ifdef USE_POWER_PINS
   .VPWR(vccd1),
   .VGND(vssd1),
  `endif
-  .A(la_data_in[7]),
-  .B(la_data_in[8]),
-  .Y(la_data_out[9]),
-);
-XNOR2X1 XNOR2X1(
- `ifdef USE_POWER_PINS
-  .VPWR(vccd1),
-  .VGND(vssd1),
- `endif
-  .A(la_data_in[10]),
-  .B(la_data_in[11]),
+  .A(la_data_in[9]),
+  .B(la_data_in[10]),
+  .C(la_data_in[11]),
   .Y(la_data_out[12]),
 );
-XOR2X1 XOR2X1(
+OAI22X1 OAI22X1(
  `ifdef USE_POWER_PINS
   .VPWR(vccd1),
   .VGND(vssd1),
  `endif
   .A(la_data_in[13]),
   .B(la_data_in[14]),
-  .Y(la_data_out[15]),
+  .C(la_data_in[15]),
+  .D(la_data_in[16]),
+  .Y(la_data_out[17]),
+);
+OR2X1 OR2X1(
+ `ifdef USE_POWER_PINS
+  .VPWR(vccd1),
+  .VGND(vssd1),
+ `endif
+  .A(la_data_in[18]),
+  .B(la_data_in[19]),
+  .Y(la_data_out[20]),
+);
+OR2X2 OR2X2(
+ `ifdef USE_POWER_PINS
+  .VPWR(vccd1),
+  .VGND(vssd1),
+ `endif
+  .A(la_data_in[21]),
+  .B(la_data_in[22]),
+  .Y(la_data_out[23]),
+);
+XNOR2X1 XNOR2X1(
+ `ifdef USE_POWER_PINS
+  .VPWR(vccd1),
+  .VGND(vssd1),
+ `endif
+  .A(la_data_in[24]),
+  .B(la_data_in[25]),
+  .Y(la_data_out[26]),
+);
+XOR2X1 XOR2X1(
+ `ifdef USE_POWER_PINS
+  .VPWR(vccd1),
+  .VGND(vssd1),
+ `endif
+  .A(la_data_in[27]),
+  .B(la_data_in[28]),
+  .Y(la_data_out[29]),
 );
 assign io_oeb[0] = 1'b1;
 assign io_oeb[1] = 1'b1;
@@ -256,11 +289,11 @@
 assign io_oeb[29] = 1'b1;
 assign io_oeb[30] = 1'b0;
 assign io_oeb[31] = 1'b1;
-assign io_oeb[32] = 1'b1;
+assign io_oeb[32] = 1'b0;
 assign io_oeb[33] = 1'b1;
-assign io_oeb[34] = 1'b0;
+assign io_oeb[34] = 1'b1;
 assign io_oeb[35] = 1'b1;
-assign io_oeb[36] = 1'b1;
-assign io_oeb[37] = 1'b0;
+assign io_oeb[36] = 1'b0;
+assign io_oeb[37] = 1'b1;
 endmodule
 `default_nettype wire