blob: 5c2d879093a87e55eaac81056a4be7922eb99499 [file] [log] [blame]
description: "At Libresilicon we have been working for several years on making chipdesign and production available to a wider public. One big step is now to automatically generate standard cell libraries just from the DRC rules and a given or even generated netlist."
foundry: "SkyWater"
git_url: ""
organization: "Libresilicon Association"
organization_url: ""
owner: "Philipp Guehring"
process: "SKY130"
project_name: "automaticstandardcelllibrary"
project_id: "00000150"
- "Open MPW"
- "Test Wafer"
- "MPW2"
- "Libresilicon"
- "Librecell"
- "StdCellLib"
category: "Test Wafer"
top_level_netlist: "caravel/verilog/gl/caravel.v"
user_level_netlist: "verilog/gl/user_project_wrapper.v"
version: "1.00"
cover_image: "docs/source/_static/user_proj_example.gds.png"