diff --git a/info.yaml b/info.yaml
index bdd53ba..965564c 100644
--- a/info.yaml
+++ b/info.yaml
@@ -1,18 +1,22 @@
 ---
 project:
-  description: "A template SoC for Google sponsored Open MPW shuttles for SKY130."
+  description: "At Libresilicon we have been working for several years on making chipdesign and production available to a wider public. One big step is now to automatically generate standard cell libraries just from the DRC rules and a given or even generated netlist."
   foundry: "SkyWater"
-  git_url: "https://github.com/efabless/caravel_project_example.git"
-  organization: "Efabless"
-  organization_url: "http://efabless.com"
-  owner: "Tim Edwards"
+  git_url: "https://github.com/thesourcerer8/caravel_stdcelllib_stdcells_project.git"
+  organization: "Libresilicon Association"
+  organization_url: "http://libresilicon.com"
+  owner: "Philipp Guehring"
   process: "SKY130"
   project_name: "Caravel"
   project_id: "00000000"
   tags:
     - "Open MPW"
-    - "Test Harness"
-  category: "Test Harness"
+    - "Test Wafer"
+    - "MPW2"
+    - "Libresilicon"
+    - "Librecell"
+    - "StdCellLib"
+  category: "Test Wafer"
   top_level_netlist: "caravel/verilog/gl/caravel.v"
   user_level_netlist: "verilog/gl/user_project_wrapper.v"
   version: "1.00"