/root/stdcelllib/Makefile
/root/stdcelllib/env.sh
/root/stdcelllib/build.html
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/root/stdcelllib/cells/lef/CLKBUF2.lef.temp
/root/stdcelllib/cells/lef/HAX1.lef.beforemagic
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/root/stdcelllib/cells/lef/SUTHERLAND1989.lef.beforemagic
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/root/stdcelllib/cells/lef/CLKBUF1.lef.beforemagic
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/root/stdcelllib/cells/lef/OAI22X1.lef.beforemagic
/root/stdcelllib/cells/lef/OR2X2.lef.beforemagic
/root/stdcelllib/cells/lef/INVX2.lef.beforemagic
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/root/stdcelllib/cells/lef/NAND2X1.lef.beforemagic
/root/stdcelllib/cells/lef/INVX4.lef.temp
/root/stdcelllib/cells/lef/ASYNC3.lef.beforemagic
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/root/stdcelllib/cells/lef/AOI21X1.lef.temp
/root/stdcelllib/cells/lef/XNOR2X1.lef.temp
/root/stdcelllib/cells/lef/XNOR2X1.lef.beforemagic
/root/stdcelllib/cells/cell/AOI22X1.cell
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/root/stdcelllib/cells/cell/OR2X2.cell
/root/stdcelllib/cells/cell/CLKBUF3.cell
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/root/stdcelllib/cells/cell/PADINOUT.cell
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/root/stdcelllib/cells/cell/MARTIN1989.cell
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/root/stdcelllib/cells/cell/CLKBUF2.cell
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/root/stdcelllib/cells/cell/XOR2X1.cell
/root/stdcelllib/cells/cell/PADOUT.cell
/root/stdcelllib/cells/cell/BUFX2.cell
/root/stdcelllib/cells/cell/INVX1.cell
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/root/stdcelllib/cells/cell/HAX1.cell
/root/stdcelllib/cells/cell/AND2X1.cell
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/root/stdcelllib/cells/sp/AND2X1.sp
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/root/stdcelllib/cells/sp/MARTIN1989.sp
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/root/stdcelllib/cells/sp/SUTHERLAND1989.sp
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/root/stdcelllib/cells/sp/VANBERKEL1991.sp
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/root/stdcelllib/docs/environment.yml
/root/stdcelllib/docs/Makefile
/root/stdcelllib/docs/source/index.rst
/root/stdcelllib/docs/source/conf.py
/root/stdcelllib/verilog/dv/Makefile
/root/stdcelllib/verilog/dv/la_test2/la_test2_tb.v
/root/stdcelllib/verilog/dv/la_test2/la_test2.c
/root/stdcelllib/verilog/dv/la_test2/Makefile
/root/stdcelllib/verilog/dv/la_test1/la_test1.c
/root/stdcelllib/verilog/dv/la_test1/Makefile
/root/stdcelllib/verilog/dv/la_test1/la_test1_tb.v
/root/stdcelllib/verilog/dv/io_ports/Makefile
/root/stdcelllib/verilog/dv/io_ports/io_ports_tb.v
/root/stdcelllib/verilog/dv/io_ports/io_ports.c
/root/stdcelllib/verilog/dv/mprj_stimulus/Makefile
/root/stdcelllib/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
/root/stdcelllib/verilog/dv/mprj_stimulus/mprj_stimulus.c
/root/stdcelllib/verilog/dv/wb_port/wb_port_tb.v
/root/stdcelllib/verilog/dv/wb_port/Makefile
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/root/stdcelllib/verilog/rtl/user_proj_cells.v
/root/stdcelllib/verilog/rtl/uprj_netlists.v
/root/stdcelllib/verilog/rtl/user_proj_example.v
/root/stdcelllib/verilog/rtl/user_project_wrapper.v
/root/stdcelllib/mag/.magicrc
/root/stdcelllib/scripts/viewer.pl
/root/stdcelllib/scripts/generator.pl
/root/stdcelllib/scripts/cells.pl
/root/stdcelllib/scripts/placement.pl
/root/stdcelllib/scripts/removeDRCcells.pl
/root/stdcelllib/scripts/deploy2caravel.sh
/root/stdcelllib/scripts/testgen.pl
/root/stdcelllib/scripts/gitpush.sh
/root/stdcelllib/scripts/feedback2mag.pl
/root/stdcelllib/scripts/drcexpander.pl
/root/stdcelllib/openlane/Makefile
/root/stdcelllib/openlane/user_proj_example/config.json
/root/stdcelllib/openlane/user_proj_example/config.tcl
/root/stdcelllib/openlane/user_project_wrapper/config.json
/root/stdcelllib/openlane/user_project_wrapper/config.tcl