diff --git a/docs/source/index.rst b/docs/source/index.rst
index ba8a11f..15a0a03 100644
--- a/docs/source/index.rst
+++ b/docs/source/index.rst
@@ -454,7 +454,7 @@
 -  ✔️ Top level macro is named ``user_project_wrapper``.
 -  ✔️ Full Chip Simulation passes for RTL and GL (gate-level)
 -  ✔️ The hardened Macros are LVS and DRC clean
--  ✔️ The project contains a gate-level netlist for the user project wrapper at verilog/gl/user_project_wrapper.v
+-  ✔️ The project contains a gate-level netlist for ``user_project_wrapper`` at verilog/gl/user_project_wrapper.v
 -  ✔️ The hardened ``user_project_wrapper`` adheres to the same pin
    order specified at
    `pin\_order <https://github.com/efabless/caravel/blob/master/openlane/user_project_wrapper_empty/pin_order.cfg>`__