diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl
index 61512d4..eaa5d29 100755
--- a/openlane/user_proj_example/config.tcl
+++ b/openlane/user_proj_example/config.tcl
@@ -70,3 +70,6 @@
 
 # set ::env(GLB_RT_OBS) "met2 0 3519 2920 3540" # Might be needed for precheck
 
+# The following is a workaround on the extraction issue with the power rails in the Libresilicon cells. This should be removed when the reason has been identified and solved:
+set ::env(QUIT_ON_ILLEGAL_OVERLAPS) 1
+