2021-11-15 08:48:10 - [INFO] - {{Project Git Info}} Repository: https://github.com/thesourcerer8/caravel_stdcelllib_stdcells_project.git | Branch: main | Commit: 75868751a63d26daa930deca3795a2962458af37
2021-11-15 08:48:10 - [INFO] - {{EXTRACTING GDS}} Extracting GDS files in: stdcelllib
2021-11-15 08:48:10 - [INFO] - {{Project GDS Info}} user_project_wrapper: 49f9c5dac4e61a5e1631e9b7f3ef3d8657912e02
2021-11-15 08:48:10 - [INFO] - {{Tools Info}} KLayout: v0.27.3 | Magic: v8.3.220
2021-11-15 08:48:10 - [INFO] - {{PDKs Info}} Open PDKs: 14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad | Skywater PDK: c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
2021-11-15 08:48:10 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in 'stdcelllib/jobs/mpw_precheck/c7eb4be5-55f6-439f-9995-f970089da357/logs'
2021-11-15 08:48:10 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: License Manifest Makefile Default Documentation Consistency XOR Magic DRC Klayout FEOL Klayout BEOL Klayout Offgrid Klayout Metal Minimum Clear Area Density Klayout Pin Label Purposes Overlapping Drawing Klayout ZeroArea
2021-11-15 08:48:10 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 14: License
2021-11-15 08:48:11 - [INFO] - An approved LICENSE (Apache-2.0) was found in stdcelllib.
2021-11-15 08:48:11 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
2021-11-15 08:48:12 - [INFO] - An approved LICENSE (Apache-2.0) was found in stdcelllib.
2021-11-15 08:48:12 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
2021-11-15 08:48:12 - [ERROR] - SPDX COMPLIANCE SYMLINK FILE NOT FOUND in stdcelllib/verilog/dv/io_ports/libs.ref
2021-11-15 08:48:12 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 234 non-compliant file(s) with the SPDX Standard.
2021-11-15 08:48:12 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['stdcelllib/Makefile', 'stdcelllib/env.sh', 'stdcelllib/build.html', 'stdcelllib/cells/mag/OR2X2.mag.beforemagic', 'stdcelllib/cells/mag/XNOR2X1.mag.beforemagic', 'stdcelllib/cells/mag/ASYNC3.mag.beforemagic', 'stdcelllib/cells/mag/VANBERKEL1991.mag.beforemagic', 'stdcelllib/cells/mag/NOR2X1.mag.beforemagic', 'stdcelllib/cells/mag/AOI22X1.mag.beforemagic', 'stdcelllib/cells/mag/INV.mag.beforemagic', 'stdcelllib/cells/mag/INVX2.mag.beforemagic', 'stdcelllib/cells/mag/ASYNC2.mag.beforemagic', 'stdcelllib/cells/mag/OAI22X1.mag.beforemagic', 'stdcelllib/cells/mag/MUX2X1.mag.beforemagic', 'stdcelllib/cells/mag/BUFX2.mag.beforemagic']
2021-11-15 08:48:12 - [INFO] - For the full SPDX compliance report check: stdcelllib/jobs/mpw_precheck/c7eb4be5-55f6-439f-9995-f970089da357/logs/spdx_compliance_report.log
2021-11-15 08:48:12 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 14: Manifest
2021-11-15 08:48:12 - [INFO] - Caravel version matches, for the full report check: stdcelllib/jobs/mpw_precheck/c7eb4be5-55f6-439f-9995-f970089da357/logs/manifest_check.log
2021-11-15 08:48:12 - [INFO] - {{MANIFEST CHECKS PASSED}} Manifest Checks Passed. Caravel version matches.
2021-11-15 08:48:12 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 14: Makefile
2021-11-15 08:48:12 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
2021-11-15 08:48:12 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 14: Default
2021-11-15 08:48:12 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
2021-11-15 08:48:13 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
2021-11-15 08:48:13 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 14: Documentation
2021-11-15 08:48:13 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
2021-11-15 08:48:13 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 14: Consistency
2021-11-15 08:48:13 - [INFO] - Trying to get file https://raw.githubusercontent.com/efabless/caravel/ca9025570d8180598301d874117a63d372d4243c/verilog/rtl/__user_project_wrapper.v
2021-11-15 08:48:13 - [INFO] - Got file https://raw.githubusercontent.com/efabless/caravel/ca9025570d8180598301d874117a63d372d4243c/verilog/rtl/__user_project_wrapper.v
2021-11-15 08:48:13 - [INFO] - Trying to get file https://raw.githubusercontent.com/efabless/caravel/ca9025570d8180598301d874117a63d372d4243c/verilog/rtl/defines.v
2021-11-15 08:48:13 - [INFO] - Got file https://raw.githubusercontent.com/efabless/caravel/ca9025570d8180598301d874117a63d372d4243c/verilog/rtl/defines.v
2021-11-15 08:48:18 - [INFO] - HIERARCHY CHECK PASSED: Module user_project_wrapper is instantiated in caravel. 
2021-11-15 08:48:18 - [INFO] - COMPLEXITY CHECK PASSED: Netlist caravel contains at least 8 instances (46 instances). 
2021-11-15 08:48:18 - [INFO] - MODELING CHECK PASSED: Netlist caravel is structural.
2021-11-15 08:48:18 - [INFO] - SUBMODULE HOOKS CHECK PASSED: All module ports for user_project_wrapper are correctly connected in the top level netlist caravel.
2021-11-15 08:48:18 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in caravel are connected to power
2021-11-15 08:48:18 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravel netlist passed all consistency checks.
2021-11-15 08:48:18 - [INFO] - PORTS CHECK PASSED: Netlist user_project_wrapper ports match the golden wrapper ports
2021-11-15 08:48:18 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_project_wrapper contains at least 1 instances (1 instances). 
2021-11-15 08:48:18 - [INFO] - MODELING CHECK PASSED: Netlist user_project_wrapper is structural.
2021-11-15 08:48:18 - [INFO] - LAYOUT CHECK PASSED: The GDS layout for user_project_wrapper matches the provided structural netlist.
2021-11-15 08:48:18 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in user_project_wrapper are connected to power
2021-11-15 08:48:18 - [INFO] - PORT TYPES CHECK PASSED: Netlist user_project_wrapper port types match the golden wrapper port types.
2021-11-15 08:48:18 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} user_project_wrapper netlist passed all consistency checks.
2021-11-15 08:48:18 - [INFO] - {{CONSISTENCY CHECK PASSED}} The user netlist and the top netlist are valid.
2021-11-15 08:48:18 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 14: XOR
2021-11-15 08:48:18 - [INFO] - Trying to get file https://raw.githubusercontent.com/efabless/caravel/ca9025570d8180598301d874117a63d372d4243c/gds/user_project_wrapper_empty.gds.gz
2021-11-15 08:48:18 - [INFO] - Got file https://raw.githubusercontent.com/efabless/caravel/ca9025570d8180598301d874117a63d372d4243c/gds/user_project_wrapper_empty.gds.gz
2021-11-15 08:48:24 - [INFO] - {XOR CHECK UPDATE} Total XOR differences: 0, for more details view stdcelllib/jobs/mpw_precheck/c7eb4be5-55f6-439f-9995-f970089da357/outputs/user_project_wrapper.xor.gds
2021-11-15 08:48:24 - [INFO] - {{XOR CHECK PASSED}} The GDS file has no XOR violations.
2021-11-15 08:48:24 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 14: Magic DRC
2021-11-15 08:49:57 - [INFO] - 0 DRC violations
2021-11-15 08:49:57 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2021-11-15 08:49:57 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 14: Klayout FEOL
2021-11-15 08:50:08 - [INFO] - No DRC Violations found
2021-11-15 08:50:08 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2021-11-15 08:50:08 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 14: Klayout BEOL
2021-11-15 08:53:00 - [INFO] - No DRC Violations found
2021-11-15 08:53:00 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2021-11-15 08:53:00 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 14: Klayout Offgrid
2021-11-15 08:53:20 - [INFO] - No DRC Violations found
2021-11-15 08:53:20 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2021-11-15 08:53:20 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 14: Klayout Metal Minimum Clear Area Density
2021-11-15 08:53:26 - [INFO] - No DRC Violations found
2021-11-15 08:53:26 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2021-11-15 08:53:26 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 14: Klayout Pin Label Purposes Overlapping Drawing
2021-11-15 08:53:30 - [INFO] - No DRC Violations found
2021-11-15 08:53:30 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2021-11-15 08:53:30 - [INFO] - {{STEP UPDATE}} Executing Check 14 of 14: Klayout ZeroArea
2021-11-15 08:53:32 - [INFO] - No DRC Violations found
2021-11-15 08:53:32 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2021-11-15 08:53:32 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in 'stdcelllib/jobs/mpw_precheck/c7eb4be5-55f6-439f-9995-f970089da357/logs'
2021-11-15 08:53:32 - [INFO] - {{SUCCESS}} All Checks Passed !!!