)]}' { "commit": "4bde49927793ab5877c4d5e3d1e77bd4dc1012c2", "tree": "1a4a6679a9a23c0f5385407bf47f3266ca6d34c4", "parents": [ "d7040ce84dc69dedf93698925ee8e7f477f2ae8b" ], "author": { "name": "manarabdelaty", "email": "manarabdelatty@aucegypt.edu", "time": "Thu Sep 02 13:21:06 2021 +0200" }, "committer": { "name": "manarabdelaty", "email": "manarabdelatty@aucegypt.edu", "time": "Thu Sep 02 13:21:06 2021 +0200" }, "message": "Add SPDX to GL\n", "tree_diff": [ { "type": "modify", "old_id": "1ff3547daafe42f83c05ddc4d9bd9a264bd6cb7c", "old_mode": 33188, "old_path": "verilog/gl/user_proj_example.v", "new_id": "19f49ae4eaad6fd5ceb8c31653d11ae2258ea7b6", "new_mode": 33188, "new_path": "verilog/gl/user_proj_example.v" }, { "type": "modify", "old_id": "913e3ce922c4842a98b02ea061af8770132aa253", "old_mode": 33188, "old_path": "verilog/gl/user_project_wrapper.v", "new_id": "7ebcaf888785c7f0f01ee361ecb11c8e731d7dbd", "new_mode": 33188, "new_path": "verilog/gl/user_project_wrapper.v" } ] }