tree: 8ee69c292432fc09392032980766a3e5158ff358 [path history] [tgz]
  1. .github/
  2. cells/
  3. def/
  4. docs/
  5. gds/
  6. lef/
  7. mag/
  8. maglef/
  9. openlane/
  10. scripts/
  11. signoff/
  12. spi/
  13. verilog/
  14. .gitignore
  15. .gitmodules
  17. info.yaml
  19. Makefile

Caravel User Project

License UPRJ_CI Caravel Build

Libresilicon StdCellLib LS130 - SKY130 Test-wafer

This project is a test-wafer which puts various LS130 cells into the user-area of a Caravel harness for taping the LS130 cells out on the Skywater 130nm process.

The LS130 cells are generated with the flow (which uses Librecell's lclayout and lctime), using the Tech.SKY130 configuration.

The build report can be seen here: The cells were copied into this repository to avoid additional dependencies:

A generator was developed to generate a Verilog file for all the cells that places each cell once and connects it to the IOs of the harness: The script needs to be run from the Catalog directory of your StdCellLib. The output is then used as

In the end I adapted to use the cells as blackbox cells.

Build process:

git clone

cd caravel_stdcelllib_stdcells_project

Now please adapt the pathes in the file where necessary

. ./

make install # install caravel-lite

make pdk # clone and build pdk

make openlane # clone and build build openlane

scripts/ # This takes all the cells from the StdCellLib/Catalog directory and puts them on the Caravel

make user_proj_example # This builds the Caravel

Refer to README for the Caravel documentation.