)]}'
{
  "log": [
    {
      "commit": "d8253241a143da5736e822bc6e9254bffe18aaf3",
      "tree": "3b251f0a781ce8277fccb9a59d44b2ad8d5b0315",
      "parents": [
        "410704f433ace9afad2a2e62f0e9c79e3c22e31d"
      ],
      "author": {
        "name": "Tim \u0027mithro\u0027 Ansell",
        "email": "me@mith.ro",
        "time": "Thu Dec 29 23:53:50 2022 +0000"
      },
      "committer": {
        "name": "Tim \u0027mithro\u0027 Ansell",
        "email": "me@mith.ro",
        "time": "Thu Dec 29 23:53:50 2022 +0000"
      },
      "message": "Updating the shuttle_url value in `info.yaml` file.\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003cme@mith.ro\u003e\n"
    },
    {
      "commit": "410704f433ace9afad2a2e62f0e9c79e3c22e31d",
      "tree": "5193489c70bcd846f2b6631cb8368b6c85a62dc1",
      "parents": [
        "0fc9d6e86f1321d97ec487582d71c4b7b1fca1ae"
      ],
      "author": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Tue Dec 28 01:53:05 2021 +0000"
      },
      "committer": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Tue Dec 28 01:53:05 2021 +0000"
      },
      "message": "final gds \u0026 signoff results\n"
    },
    {
      "commit": "0fc9d6e86f1321d97ec487582d71c4b7b1fca1ae",
      "tree": "6f4241c3b6621538480afdc42092c9b75581a3b1",
      "parents": [
        "50c792797a048b4404d040c1b7207477e59cb722"
      ],
      "author": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Tue Dec 28 01:29:26 2021 +0000"
      },
      "committer": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Tue Dec 28 01:29:26 2021 +0000"
      },
      "message": "final gds oasis\n"
    },
    {
      "commit": "50c792797a048b4404d040c1b7207477e59cb722",
      "tree": "a5cc4b4c067309e47a00250109aa2b17dbddc31e",
      "parents": [
        "2c800e2befe991e738c73f0c6f417847be523dae"
      ],
      "author": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Mon Dec 27 09:22:31 2021 +0000"
      },
      "committer": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Mon Dec 27 09:22:31 2021 +0000"
      },
      "message": "final gds \u0026 signoff results\n"
    },
    {
      "commit": "2c800e2befe991e738c73f0c6f417847be523dae",
      "tree": "a3da6bbd630da2192543ed391a0a1363fb5daf38",
      "parents": [
        "760a31cfdff6ff001b2924f2c0036f61f69e7012"
      ],
      "author": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Mon Dec 27 08:56:32 2021 +0000"
      },
      "committer": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Mon Dec 27 08:56:32 2021 +0000"
      },
      "message": "final gds oasis\n"
    },
    {
      "commit": "760a31cfdff6ff001b2924f2c0036f61f69e7012",
      "tree": "cd8afb1997b0b15b48e9d7157008b4a0934d32b0",
      "parents": [
        "53ca32ecf6413df49d9b898941145503caf4b8ca"
      ],
      "author": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Fri Dec 10 01:27:36 2021 +0000"
      },
      "committer": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Fri Dec 10 01:27:36 2021 +0000"
      },
      "message": "final gds oasis\n"
    },
    {
      "commit": "53ca32ecf6413df49d9b898941145503caf4b8ca",
      "tree": "c601df671104697b8e6451d088972832c457f86c",
      "parents": [
        "aee052147f5f856ac2722b47945cad7f642796b0"
      ],
      "author": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Thu Dec 09 17:16:23 2021 +0000"
      },
      "committer": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Thu Dec 09 17:16:23 2021 +0000"
      },
      "message": "final gds oasis\n"
    },
    {
      "commit": "aee052147f5f856ac2722b47945cad7f642796b0",
      "tree": "144962c9105b4f717c4f5ca23b5a96d1917467ee",
      "parents": [
        "180cf1c40d5c3922bd351bd7782f8662c69b6209"
      ],
      "author": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Wed Dec 08 05:49:54 2021 +0000"
      },
      "committer": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Wed Dec 08 05:49:54 2021 +0000"
      },
      "message": "tapeout.log\n"
    },
    {
      "commit": "180cf1c40d5c3922bd351bd7782f8662c69b6209",
      "tree": "cb86e01f46ca18a0fd31dcdd97b7123550ff3d4f",
      "parents": [
        "9c0d4c2ef362220ee9494a40ed18cc1e1082f2cc"
      ],
      "author": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Wed Dec 08 05:36:39 2021 +0000"
      },
      "committer": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Wed Dec 08 05:36:39 2021 +0000"
      },
      "message": "final gds oasis\n"
    },
    {
      "commit": "9c0d4c2ef362220ee9494a40ed18cc1e1082f2cc",
      "tree": "7035fc5747724e57fa2f731d6bb4e92dd30b80df",
      "parents": [
        "ea71d4fc2fa273d95a109b17e16f0d249f4dbc71"
      ],
      "author": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Mon Dec 06 04:01:24 2021 +0000"
      },
      "committer": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Mon Dec 06 04:01:24 2021 +0000"
      },
      "message": "tapeout.log\n"
    },
    {
      "commit": "ea71d4fc2fa273d95a109b17e16f0d249f4dbc71",
      "tree": "90ed716fdddfb3477fb1432a3979ba435126250b",
      "parents": [
        "b5041b22884c2004e8203e74567a23de5fc86efa"
      ],
      "author": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Mon Dec 06 03:48:19 2021 +0000"
      },
      "committer": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Mon Dec 06 03:48:19 2021 +0000"
      },
      "message": "final gds oasis\n"
    },
    {
      "commit": "b5041b22884c2004e8203e74567a23de5fc86efa",
      "tree": "2396cd36049913561e9ef0a7fc7ce39ce01b80a0",
      "parents": [
        "bacdec24ef337f2aa942a24465595cdc26385f69"
      ],
      "author": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Fri Dec 03 08:05:26 2021 +0000"
      },
      "committer": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Fri Dec 03 08:05:26 2021 +0000"
      },
      "message": "tapeout.log\n"
    },
    {
      "commit": "bacdec24ef337f2aa942a24465595cdc26385f69",
      "tree": "69bb1044c0f95176bef05b91123ba5d1ab59aebe",
      "parents": [
        "c381e8088658ee41372560f2cbd8f36eda0d5f3c"
      ],
      "author": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Fri Dec 03 08:04:46 2021 +0000"
      },
      "committer": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Fri Dec 03 08:04:46 2021 +0000"
      },
      "message": "final gds oasis\n"
    },
    {
      "commit": "c381e8088658ee41372560f2cbd8f36eda0d5f3c",
      "tree": "30757c3b67792e8bf1a92c81567da3cb0ba10030",
      "parents": [
        "28d28fa32a05bac2331f15987316acc93447e95d"
      ],
      "author": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Fri Aug 20 04:56:50 2021 +0000"
      },
      "committer": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Fri Aug 20 04:56:50 2021 +0000"
      },
      "message": "final gds oasis\n"
    },
    {
      "commit": "28d28fa32a05bac2331f15987316acc93447e95d",
      "tree": "8d0b4c68e88bba2ce9005ae8373e618649f82bb0",
      "parents": [
        "5a6b84cda685923cb0f0774cc10c2833c447b170"
      ],
      "author": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Thu Aug 19 07:02:33 2021 +0000"
      },
      "committer": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Thu Aug 19 07:02:33 2021 +0000"
      },
      "message": "final gds oasis\n"
    },
    {
      "commit": "5a6b84cda685923cb0f0774cc10c2833c447b170",
      "tree": "79b5e04aefd229a42c45056af711e7198d442145",
      "parents": [
        "d20a7104f1605b245e20f114e98bec56095b7240"
      ],
      "author": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Wed Aug 18 23:36:35 2021 +0000"
      },
      "committer": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Wed Aug 18 23:36:35 2021 +0000"
      },
      "message": "tapeout.log\n"
    },
    {
      "commit": "d20a7104f1605b245e20f114e98bec56095b7240",
      "tree": "11621b3e3f7078af5cc68c7f22df49e78d528f52",
      "parents": [
        "06df673f190876a39e0d5e49e2c36e95c290db9a"
      ],
      "author": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Wed Aug 18 23:22:41 2021 +0000"
      },
      "committer": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Wed Aug 18 23:22:41 2021 +0000"
      },
      "message": "final gds oasis\n"
    },
    {
      "commit": "06df673f190876a39e0d5e49e2c36e95c290db9a",
      "tree": "066b4b9d2167e5e11a17384fbc1fc1f69532c67d",
      "parents": [
        "65779ede86fbd1f7f76c42892276e6ba1dd079db"
      ],
      "author": {
        "name": "Mehdi Saligane",
        "email": "mehdi@vlsipool-rhel7-01.eecs.umich.edu",
        "time": "Wed Aug 18 17:32:16 2021 -0400"
      },
      "committer": {
        "name": "Mehdi Saligane",
        "email": "mehdi@vlsipool-rhel7-01.eecs.umich.edu",
        "time": "Wed Aug 18 17:32:16 2021 -0400"
      },
      "message": "updated SRAM with metal fix\n"
    },
    {
      "commit": "65779ede86fbd1f7f76c42892276e6ba1dd079db",
      "tree": "ce8ea98ec29d62938cb154b20388d7d50893e52b",
      "parents": [
        "f59ed79a9c47c2665c7c966969bd209e115e637a"
      ],
      "author": {
        "name": "Mehdi Saligane",
        "email": "mehdi@vlsipool-j06.eecs.umich.edu",
        "time": "Tue Aug 10 20:45:05 2021 -0400"
      },
      "committer": {
        "name": "Mehdi Saligane",
        "email": "mehdi@vlsipool-j06.eecs.umich.edu",
        "time": "Tue Aug 10 20:45:05 2021 -0400"
      },
      "message": "fix latch-up and tapcells insertion\n"
    },
    {
      "commit": "f59ed79a9c47c2665c7c966969bd209e115e637a",
      "tree": "871eb6312240acb843b3626546804c01288b51fa",
      "parents": [
        "4140650fd05bc5bf073d0f9e8338f3804143f377"
      ],
      "author": {
        "name": "Mehdi Saligane",
        "email": "mehdi@vlsipool-j06.eecs.umich.edu",
        "time": "Fri Aug 06 12:08:48 2021 -0400"
      },
      "committer": {
        "name": "Mehdi Saligane",
        "email": "mehdi@vlsipool-j06.eecs.umich.edu",
        "time": "Fri Aug 06 12:08:48 2021 -0400"
      },
      "message": "fixed hold timing of OT and power routing\n"
    },
    {
      "commit": "4140650fd05bc5bf073d0f9e8338f3804143f377",
      "tree": "18b1072d2fdfb9910244dda30ef90b167925b317",
      "parents": [
        "d64a3bc4062ce9e2c9a3f763d857d618f2e0f148"
      ],
      "author": {
        "name": "Mehdi Saligane",
        "email": "mehdi@vlsipool-j06.eecs.umich.edu",
        "time": "Thu Aug 05 06:14:20 2021 -0400"
      },
      "committer": {
        "name": "Mehdi Saligane",
        "email": "mehdi@vlsipool-j06.eecs.umich.edu",
        "time": "Thu Aug 05 06:14:20 2021 -0400"
      },
      "message": "updated select for LDOs and power routing\n"
    },
    {
      "commit": "d64a3bc4062ce9e2c9a3f763d857d618f2e0f148",
      "tree": "bc75821abd5115bd183f3d90850c9caf0ac3ec93",
      "parents": [
        "05657df1a714cfe0c46c7efd0e0422ff48975c24"
      ],
      "author": {
        "name": "Peijun Hou",
        "email": "peijunh@vlsipool-j01.eecs.umich.edu",
        "time": "Mon Aug 02 11:14:22 2021 -0400"
      },
      "committer": {
        "name": "Peijun Hou",
        "email": "peijunh@vlsipool-j01.eecs.umich.edu",
        "time": "Mon Aug 02 11:14:22 2021 -0400"
      },
      "message": "drc clean LDO, and wider analog wire, double power pad\n"
    },
    {
      "commit": "05657df1a714cfe0c46c7efd0e0422ff48975c24",
      "tree": "429f656573abb3f9e80e44f5965a2360b41aacdd",
      "parents": [
        "b81e1be67607390110be0c5efa62106246fb2b36"
      ],
      "author": {
        "name": "Mehdi Saligane",
        "email": "mehdi@vlsipool-j06.eecs.umich.edu",
        "time": "Thu Jul 29 13:35:37 2021 -0400"
      },
      "committer": {
        "name": "Mehdi Saligane",
        "email": "mehdi@vlsipool-j06.eecs.umich.edu",
        "time": "Thu Jul 29 13:35:37 2021 -0400"
      },
      "message": "1st commit MPW-II including LDOs, Opentitan SoC and voltage references\n"
    },
    {
      "commit": "b81e1be67607390110be0c5efa62106246fb2b36",
      "tree": "414f33d4d633fff3d99dd42503470bc4342df824",
      "parents": [
        "517439c72ee9d7cc6085394029dbf379ad31a20f"
      ],
      "author": {
        "name": "Mehdi Saligane",
        "email": "mehdi@vlsipool-j06.eecs.umich.edu",
        "time": "Thu Jul 29 13:34:59 2021 -0400"
      },
      "committer": {
        "name": "Mehdi Saligane",
        "email": "mehdi@vlsipool-j06.eecs.umich.edu",
        "time": "Thu Jul 29 13:34:59 2021 -0400"
      },
      "message": "rm large gds files\n"
    },
    {
      "commit": "517439c72ee9d7cc6085394029dbf379ad31a20f",
      "tree": "9b13503acdac26207b34b9b6e8dd15f27c698ad8",
      "parents": [
        "67640ef400d8df3cfb0a49c79a3b7e14136869b5"
      ],
      "author": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Sun Jun 20 14:12:18 2021 -0700"
      },
      "committer": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Sun Jun 20 14:12:18 2021 -0700"
      },
      "message": "fix check_default missing ENV variables\n"
    },
    {
      "commit": "67640ef400d8df3cfb0a49c79a3b7e14136869b5",
      "tree": "d5b31e03dc5a1dd83ac6a09d6b78514d370cdc2b",
      "parents": [
        "c68f39ed84d85cb037c7ef96bc9d29c3d2e62edd"
      ],
      "author": {
        "name": "Git bot",
        "email": "bot@noreply.github.com",
        "time": "Sat May 08 18:24:21 2021 +0000"
      },
      "committer": {
        "name": "Git bot",
        "email": "bot@noreply.github.com",
        "time": "Sat May 08 18:24:21 2021 +0000"
      },
      "message": "Auto updated submodule references\n"
    },
    {
      "commit": "c68f39ed84d85cb037c7ef96bc9d29c3d2e62edd",
      "tree": "b4c3d61cf5221ad7e3544eaca6d53222afca1625",
      "parents": [
        "13f142e8fd4ae0a62f4e13bced1c33601b8b47b7"
      ],
      "author": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Sat May 08 13:47:45 2021 -0400"
      },
      "committer": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Sat May 08 13:47:45 2021 -0400"
      },
      "message": "Updated the documentation to include a description of the power-on-reset\ncircuit and the completed user project example.\n"
    },
    {
      "commit": "13f142e8fd4ae0a62f4e13bced1c33601b8b47b7",
      "tree": "0bdef255b8c547f5c536504f4eb1dd01fe701c4c",
      "parents": [
        "520ff4ac3cd703accd51b465ab484a7aa15f6a0e"
      ],
      "author": {
        "name": "Manar",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Sat May 08 18:43:17 2021 +0200"
      },
      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Sat May 08 18:43:17 2021 +0200"
      },
      "message": "Update index.rst"
    },
    {
      "commit": "520ff4ac3cd703accd51b465ab484a7aa15f6a0e",
      "tree": "94dc6b20d546e82230b626224b2597f84f132609",
      "parents": [
        "a119592c1a186217c84b939b5698462870cc4f67"
      ],
      "author": {
        "name": "Manar",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Sat May 08 18:39:47 2021 +0200"
      },
      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Sat May 08 18:39:47 2021 +0200"
      },
      "message": "Update index.rst"
    },
    {
      "commit": "a119592c1a186217c84b939b5698462870cc4f67",
      "tree": "e04aefef9c029be82ac24022b6ad7663f6845d86",
      "parents": [
        "dd3d811e1d19aff4136662b7550e25a8dac07f6d"
      ],
      "author": {
        "name": "Manar",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Sat May 08 18:38:16 2021 +0200"
      },
      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Sat May 08 18:38:16 2021 +0200"
      },
      "message": "Update index.rst"
    },
    {
      "commit": "dd3d811e1d19aff4136662b7550e25a8dac07f6d",
      "tree": "25983ce662c2bcd49d9e0e7a2672aa355eb5b058",
      "parents": [
        "55c9fffddc8a42dcb2dc5829e32ef5c093bf535d"
      ],
      "author": {
        "name": "manarabdelaty",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Sat May 08 18:32:32 2021 +0200"
      },
      "committer": {
        "name": "manarabdelaty",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Sat May 08 18:32:32 2021 +0200"
      },
      "message": "Doc updates\n"
    },
    {
      "commit": "55c9fffddc8a42dcb2dc5829e32ef5c093bf535d",
      "tree": "4e989c2a0404b166a35163445c680c41c6c13af4",
      "parents": [
        "f9e592bc41b4a6f1f5eda235d6eb7d603b0cff85",
        "9e46db5d213d6edc015994991db0082d65affe91"
      ],
      "author": {
        "name": "manarabdelaty",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Sat May 08 16:30:35 2021 +0200"
      },
      "committer": {
        "name": "manarabdelaty",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Sat May 08 16:30:35 2021 +0200"
      },
      "message": "Merge branch \u0027main\u0027 of https://github.com/efabless/caravel_analog_user into main\n"
    },
    {
      "commit": "9e46db5d213d6edc015994991db0082d65affe91",
      "tree": "fb4840663df7c6dbc2fdaf493e22ff273f8ff8eb",
      "parents": [
        "206bfb582751af7729539b08fccf24ced8734550"
      ],
      "author": {
        "name": "Git bot",
        "email": "bot@noreply.github.com",
        "time": "Sat May 08 00:11:46 2021 +0000"
      },
      "committer": {
        "name": "Git bot",
        "email": "bot@noreply.github.com",
        "time": "Sat May 08 00:11:46 2021 +0000"
      },
      "message": "Auto updated submodule references\n"
    },
    {
      "commit": "f9e592bc41b4a6f1f5eda235d6eb7d603b0cff85",
      "tree": "4e989c2a0404b166a35163445c680c41c6c13af4",
      "parents": [
        "3f75a898e6c38018a8bb0131c4b85a6f4110ed22"
      ],
      "author": {
        "name": "manarabdelaty",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Fri May 07 23:55:41 2021 +0200"
      },
      "committer": {
        "name": "manarabdelaty",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Fri May 07 23:55:41 2021 +0200"
      },
      "message": "Update submodule reference to caravel-lite\n"
    },
    {
      "commit": "3f75a898e6c38018a8bb0131c4b85a6f4110ed22",
      "tree": "5a9a36308134648fb7e729045e088d67b04ba2c5",
      "parents": [
        "206bfb582751af7729539b08fccf24ced8734550"
      ],
      "author": {
        "name": "manarabdelaty",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Fri May 07 23:49:05 2021 +0200"
      },
      "committer": {
        "name": "manarabdelaty",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Fri May 07 23:49:05 2021 +0200"
      },
      "message": "Update Makefile\n"
    },
    {
      "commit": "206bfb582751af7729539b08fccf24ced8734550",
      "tree": "53739c9386ed7ad2e0413ca40d39e5ab046eab96",
      "parents": [
        "b7fad20e3e2a0752fa6095591a211f4934e5b415"
      ],
      "author": {
        "name": "manarabdelaty",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Fri May 07 23:07:50 2021 +0200"
      },
      "committer": {
        "name": "manarabdelaty",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Fri May 07 23:07:50 2021 +0200"
      },
      "message": "Update run-xor.sh\n"
    },
    {
      "commit": "b7fad20e3e2a0752fa6095591a211f4934e5b415",
      "tree": "f45c9a7a9c8b3033afe67034bc421cd0692aff96",
      "parents": [
        "9b861b22e3d0ee2526249449237cfc549c8f97f9"
      ],
      "author": {
        "name": "manarabdelaty",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Fri May 07 20:32:39 2021 +0200"
      },
      "committer": {
        "name": "manarabdelaty",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Fri May 07 20:32:39 2021 +0200"
      },
      "message": "[CI] update run-xor\n"
    },
    {
      "commit": "9b861b22e3d0ee2526249449237cfc549c8f97f9",
      "tree": "ae55835f8535eb4052066f021cc96f4fed0e41f7",
      "parents": [
        "b07e4087383933ba29b719b65aa0c204080a028c"
      ],
      "author": {
        "name": "manarabdelaty",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Fri May 07 20:11:29 2021 +0200"
      },
      "committer": {
        "name": "manarabdelaty",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Fri May 07 20:11:29 2021 +0200"
      },
      "message": "Add pattern to dv Makefile and drop obselete openlane wrapper dir\n"
    },
    {
      "commit": "b07e4087383933ba29b719b65aa0c204080a028c",
      "tree": "9c42305d9b5d89567e34cab977973fa20dc7401e",
      "parents": [
        "7b7b2f635aef284c45473a9b5453515724b2f55a"
      ],
      "author": {
        "name": "Manar",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Fri May 07 20:02:40 2021 +0200"
      },
      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Fri May 07 20:02:40 2021 +0200"
      },
      "message": "Update README.md"
    },
    {
      "commit": "7b7b2f635aef284c45473a9b5453515724b2f55a",
      "tree": "74b5035b72b66785cdf04b086ae3221fcc6c1742",
      "parents": [
        "722391bf380622f58198bac88a603d305899de77"
      ],
      "author": {
        "name": "Manar",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Fri May 07 19:52:47 2021 +0200"
      },
      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Fri May 07 19:52:47 2021 +0200"
      },
      "message": "Update index.rst"
    },
    {
      "commit": "722391bf380622f58198bac88a603d305899de77",
      "tree": "5ff76a5436a1bcc715dfb64dd2b392695140f983",
      "parents": [
        "9422266caa22786588cb68bbfbec55333917d063",
        "e982ef87ac3c2f39c29f6d42a8bc06f26efbadab"
      ],
      "author": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Fri May 07 13:51:58 2021 -0400"
      },
      "committer": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Fri May 07 13:51:58 2021 -0400"
      },
      "message": "Merge branch \u0027main\u0027 of github.com:efabless/caravel_user_project_analog into main\n\nPulled a commit that happened in the last 5 seconds?\n"
    },
    {
      "commit": "e982ef87ac3c2f39c29f6d42a8bc06f26efbadab",
      "tree": "f7e6b9183077405e9d4bf229616357306e8d9b05",
      "parents": [
        "1f15094f0f239698f5619c2fc71ca7713c3e25e4"
      ],
      "author": {
        "name": "Manar",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Fri May 07 19:51:35 2021 +0200"
      },
      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Fri May 07 19:51:35 2021 +0200"
      },
      "message": "Update README.md"
    },
    {
      "commit": "9422266caa22786588cb68bbfbec55333917d063",
      "tree": "d90ff931cc5ca6481b4e62b469144932a19bffcd",
      "parents": [
        "1f15094f0f239698f5619c2fc71ca7713c3e25e4"
      ],
      "author": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Fri May 07 13:51:33 2021 -0400"
      },
      "committer": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Fri May 07 13:51:33 2021 -0400"
      },
      "message": "Modified the wrapper to extend the analog pins out 4um like the rest of\nthe (digital) pins.\n"
    },
    {
      "commit": "1f15094f0f239698f5619c2fc71ca7713c3e25e4",
      "tree": "263edc5c9a9305313b8358943ee7d7a17661d9dd",
      "parents": [
        "a1553af3fd0ad19195cff913d5eada657b4d6bdc"
      ],
      "author": {
        "name": "manarabdelaty",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Fri May 07 19:47:43 2021 +0200"
      },
      "committer": {
        "name": "manarabdelaty",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Fri May 07 19:47:43 2021 +0200"
      },
      "message": "[CI] Add github workflows for running the precheck/dv/caravan_build\n"
    },
    {
      "commit": "a1553af3fd0ad19195cff913d5eada657b4d6bdc",
      "tree": "4ebb343eb1e287f85e04ec209bedbd5789ea509d",
      "parents": [
        "892f0d2b0641ab6042b0ae18be47ce6df347cb6d"
      ],
      "author": {
        "name": "manarabdelaty",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Fri May 07 19:47:19 2021 +0200"
      },
      "committer": {
        "name": "manarabdelaty",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Fri May 07 19:47:19 2021 +0200"
      },
      "message": "Add docs dir\n"
    },
    {
      "commit": "892f0d2b0641ab6042b0ae18be47ce6df347cb6d",
      "tree": "8bdbdd8d431cb6f1e90bf48d1e7cf846c2b3357b",
      "parents": [
        "ff42addf8b91127d9fad71a351b46adab7c416d7"
      ],
      "author": {
        "name": "manarabdelaty",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Fri May 07 19:46:08 2021 +0200"
      },
      "committer": {
        "name": "manarabdelaty",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Fri May 07 19:46:08 2021 +0200"
      },
      "message": "Update Makefile\n\n- fixed simlink target\n"
    },
    {
      "commit": "ff42addf8b91127d9fad71a351b46adab7c416d7",
      "tree": "82e57abf59d26b33fb47365b2cf0473125ed2cfe",
      "parents": [
        "35111e937c8511a8b33738f0e3629158811dd0f5"
      ],
      "author": {
        "name": "manarabdelaty",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Fri May 07 19:45:49 2021 +0200"
      },
      "committer": {
        "name": "manarabdelaty",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Fri May 07 19:45:49 2021 +0200"
      },
      "message": "Update info.yaml to have the user_level_netlist point to the rtl netlist\n"
    },
    {
      "commit": "35111e937c8511a8b33738f0e3629158811dd0f5",
      "tree": "094eb763b3d4947b8b21d9e8f78874610932d52f",
      "parents": [
        "dba051e726bcb22cdf4106c3bd1fe34450daf44c"
      ],
      "author": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Fri May 07 09:52:15 2021 -0400"
      },
      "committer": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Fri May 07 09:52:15 2021 -0400"
      },
      "message": "Corrected ngspice testbenches for change in the name of the parameter\nto turn on/off the mismatch parameters.  Restored the boundary layer\nto the example user project layout, moved the boundary layer origin\nand everything else to the grid origin, and rewrote GDS for the\nexample project.\n"
    },
    {
      "commit": "dba051e726bcb22cdf4106c3bd1fe34450daf44c",
      "tree": "443918287b0e0c7c99602cf7bb016d5ec6057fbe",
      "parents": [
        "5cc020df86c96d7d61ceda22a9f5b2e5c309b0f7"
      ],
      "author": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Thu May 06 15:14:34 2021 -0400"
      },
      "committer": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Thu May 06 15:14:34 2021 -0400"
      },
      "message": "Modifications to the wrapper testbench schematic (not quite working\nyet, though).\n"
    },
    {
      "commit": "5cc020df86c96d7d61ceda22a9f5b2e5c309b0f7",
      "tree": "3839b58f5e7c2df6cc3bd737b04f59502d7460f7",
      "parents": [
        "a26abdd4844c5057f87540780fca689753eab258"
      ],
      "author": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Thu May 06 11:54:28 2021 -0400"
      },
      "committer": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Thu May 06 11:54:28 2021 -0400"
      },
      "message": "Added xschem schematic and symbol for the analog project wrapper, and a\nscript to run netgen LVS against the schematic.\n"
    },
    {
      "commit": "a26abdd4844c5057f87540780fca689753eab258",
      "tree": "42b93d7a3efde5537294072381345123dc788437",
      "parents": [
        "60e4dcb489b69ac3732a1a71efecdfeae9cc61eb"
      ],
      "author": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Thu May 06 10:36:21 2021 -0400"
      },
      "committer": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Thu May 06 10:36:21 2021 -0400"
      },
      "message": "Redid the layout for the example analog project based on the updated\nwrapper layout.  Generated GDS and extracted netlist.\n"
    },
    {
      "commit": "60e4dcb489b69ac3732a1a71efecdfeae9cc61eb",
      "tree": "1be4834144cc29e3d384574a65e161f8170a7030",
      "parents": [
        "8a1d5f234270784c8d08f6e2b0b0bf374bddf34f"
      ],
      "author": {
        "name": "manarabdelaty",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Wed May 05 23:41:20 2021 +0200"
      },
      "committer": {
        "name": "manarabdelaty",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Wed May 05 23:41:20 2021 +0200"
      },
      "message": "Update Makefile\n"
    },
    {
      "commit": "8a1d5f234270784c8d08f6e2b0b0bf374bddf34f",
      "tree": "28e86ff15d3d9c7b7135dcfd185dff90696809fa",
      "parents": [
        "6bb21656d8c3480c4577920e3b5c3b946e3d5c8b"
      ],
      "author": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Thu Apr 29 21:56:02 2021 -0400"
      },
      "committer": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Thu Apr 29 21:56:02 2021 -0400"
      },
      "message": "Corrected the info.yaml file to point to the caravan.v file as the\ntop level netlist.\n"
    },
    {
      "commit": "6bb21656d8c3480c4577920e3b5c3b946e3d5c8b",
      "tree": "dfcc6d0c729180e17ff87abb94ec7c61109d6b64",
      "parents": [
        "5ea70cb2ca8bfa33e4a4d4356799e2baf73a6400"
      ],
      "author": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Thu Apr 29 17:19:26 2021 -0400"
      },
      "committer": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Thu Apr 29 17:19:26 2021 -0400"
      },
      "message": "Added layout for the user_analog_project_wrapper example.\n"
    },
    {
      "commit": "5ea70cb2ca8bfa33e4a4d4356799e2baf73a6400",
      "tree": "9fb9c7308b25d4c57b035e6b150c5140629bee98",
      "parents": [
        "796099ed315805cfb93927d461c2a3f987660daa"
      ],
      "author": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Thu Apr 29 16:40:10 2021 -0400"
      },
      "committer": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Thu Apr 29 16:40:10 2021 -0400"
      },
      "message": "Changed the schematics so that the resistor does not set a W\nvalue, but the underlying model does anyway so this has no effect\non the LVS, which still flags property errors.\n"
    },
    {
      "commit": "796099ed315805cfb93927d461c2a3f987660daa",
      "tree": "a8daa2bef539b81d4dcd68725ac203fd681f8f4f",
      "parents": [
        "dfc24ad0d2edaec6065144b7e2600c8d02bdd592"
      ],
      "author": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Thu Apr 29 16:30:42 2021 -0400"
      },
      "committer": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Thu Apr 29 16:30:42 2021 -0400"
      },
      "message": "Corrected the schematic for the proper orientation of the topmost\ncapacitor;  the circuit now passes LVS.\n"
    },
    {
      "commit": "dfc24ad0d2edaec6065144b7e2600c8d02bdd592",
      "tree": "ab3abe59c6d04da54485c3087f85db84355b1ec6",
      "parents": [
        "fb1300105269c80e54ebc41efd883396ddbc382f"
      ],
      "author": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Thu Apr 29 16:18:51 2021 -0400"
      },
      "committer": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Thu Apr 29 16:18:51 2021 -0400"
      },
      "message": "Added xschem schematic of the POR and testbench simulations and\nresults.\n"
    },
    {
      "commit": "fb1300105269c80e54ebc41efd883396ddbc382f",
      "tree": "9508e96380dc29acf6a6c46fad52e5ce171d0bed",
      "parents": [
        "a44a60b225e824c4eeb61bd99fed0d6da25ee6b0"
      ],
      "author": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Wed Apr 28 14:08:25 2021 -0400"
      },
      "committer": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Wed Apr 28 14:08:25 2021 -0400"
      },
      "message": "Simple layout, unwired (needs modifications to the project wrapper)\n"
    },
    {
      "commit": "a44a60b225e824c4eeb61bd99fed0d6da25ee6b0",
      "tree": "f283a100f106709d046072587377dee6e5656f78",
      "parents": [
        "6af7408dc6bbf5dde440266476933cebd69f3ba7"
      ],
      "author": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Wed Apr 28 14:05:41 2021 -0400"
      },
      "committer": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Wed Apr 28 14:05:41 2021 -0400"
      },
      "message": "Preliminary work on the analog user project example.  Added verilog RTL and\ntestbench.  The design passes the testbench.\n"
    },
    {
      "commit": "6af7408dc6bbf5dde440266476933cebd69f3ba7",
      "tree": "c6e60b12e76336e2f23956900965769c1215ade5",
      "parents": [],
      "author": {
        "name": "manarabdelaty",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Mon Apr 26 14:56:35 2021 +0200"
      },
      "committer": {
        "name": "manarabdelaty",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Mon Apr 26 14:56:35 2021 +0200"
      },
      "message": "Initial commit\n"
    }
  ]
}