# User config
set ::env(DESIGN_NAME) user_analog_project_wrapper

#Add
source [glob $::env(DESIGN_DIR)/src/fixed_wrapper_cfgs.tcl]


# Change if needed
set ::env(EXTRA_LEFS) [glob $::env(DESIGN_DIR)/src/ldo_all.lef $::env(DESIGN_DIR)/src/opentitan_soc_top.lef]
set ::env(EXTRA_GDS_FILES) [glob $::env(DESIGN_DIR)/src/ldo_all.gds $::env(DESIGN_DIR)/src/opentitan_soc_top.gds]
set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/defines.v]
# set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/opentitan_soc_top.v]
set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/user_analog_project_wrapper.v]

set ::env(VERILOG_FILES_BLACKBOX) [glob $::env(DESIGN_DIR)/src/ldo_all.v $::env(DESIGN_DIR)/src/opentitan_soc_top.v]

#set ::env(SYNTH_FLAT_TOP) 1
#set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro_placement.cfg
set ::env(FP_PDN_CHECK_NODES) 0
set ::env(FP_PDN_CORE_RING) 1
set ::env(FP_PDN_ENABLE_RAILS) 0
# Fill this
set ::env(CLOCK_PERIOD) "48"
set ::env(CLOCK_PORT) "wb_clk_i"
set ::env(CLOCK_TREE_SYNTH) "0"
#set ::env(PL_RANDOM_GLB_PLACEMENT) "1"
set ::env(PL_BASIC_PLACEMENT) 1
set ::env(DIODE_INSERTION_STRATEGY) 0

## Core Margins
set ::env(BOTTOM_MARGIN_MULT) 8
set ::env(TOP_MARGIN_MULT) 8
set ::env(LEFT_MARGIN_MULT) 28
set ::env(RIGHT_MARGIN_MULT) 28

## Routing
set ::env(GLB_RT_ADJUSTMENT) 0.15

set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
if { [file exists $filename] == 1} {
        source $filename
}