)]}'
{
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        "email": "me@mith.ro",
        "time": "Thu Dec 29 23:53:48 2022 +0000"
      },
      "committer": {
        "name": "Tim \u0027mithro\u0027 Ansell",
        "email": "me@mith.ro",
        "time": "Thu Dec 29 23:53:48 2022 +0000"
      },
      "message": "Updating the shuttle_url value in `info.yaml` file.\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003cme@mith.ro\u003e\n"
    },
    {
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        "email": "jeffdi@efabless.com",
        "time": "Tue Dec 28 01:10:36 2021 +0000"
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      "message": "final gds \u0026 signoff results\n"
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        "time": "Tue Dec 28 00:47:06 2021 +0000"
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        "time": "Mon Dec 27 08:37:43 2021 +0000"
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        "time": "Mon Dec 06 03:30:10 2021 +0000"
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        "email": "jeffdi@efabless.com",
        "time": "Mon Dec 06 03:05:32 2021 +0000"
      },
      "committer": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Mon Dec 06 03:05:32 2021 +0000"
      },
      "message": "final gds oasis\n"
    },
    {
      "commit": "fc8722fe75692774e76f08d42aa7355c413d7ea7",
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      },
      "committer": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Fri Dec 03 08:03:34 2021 +0000"
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    {
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      },
      "committer": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Fri Dec 03 08:03:28 2021 +0000"
      },
      "message": "final gds oasis\n"
    },
    {
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        "time": "Wed Aug 04 08:37:35 2021 +0000"
      },
      "committer": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Wed Aug 04 08:37:35 2021 +0000"
      },
      "message": "final gds \u0026 signoff results\n"
    },
    {
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        "time": "Wed Aug 04 07:59:11 2021 +0000"
      },
      "committer": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Wed Aug 04 07:59:11 2021 +0000"
      },
      "message": "final gds oasis\n"
    },
    {
      "commit": "ed2714c50e47ec386fa1eef00658351054cea94f",
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      "author": {
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        "email": "jeffdi@efabless.com",
        "time": "Thu Jul 29 21:49:45 2021 +0000"
      },
      "committer": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Thu Jul 29 21:49:45 2021 +0000"
      },
      "message": "final gds \u0026 signoff results\n"
    },
    {
      "commit": "4256705e6e64736b01b8cc38598e79e751bf8480",
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        "email": "jeffdi@efabless.com",
        "time": "Tue Jul 27 20:12:00 2021 +0000"
      },
      "committer": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Tue Jul 27 20:12:00 2021 +0000"
      },
      "message": "final gds \u0026 signoff results\n"
    },
    {
      "commit": "c0eb08edf48b0cdd22b86564d36e10e77cfc0549",
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      "author": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Wed Jul 21 12:28:51 2021 +0000"
      },
      "committer": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Wed Jul 21 12:28:51 2021 +0000"
      },
      "message": "final gds \u0026 signoff results\n"
    },
    {
      "commit": "a6c0c41160f795e0994d59d2c2b10a02de827d6f",
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      "author": {
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        "email": "jeffdi@efabless.com",
        "time": "Sun Jul 18 14:40:06 2021 -0700"
      },
      "committer": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Sun Jul 18 14:40:06 2021 -0700"
      },
      "message": "updating ./signoff\n"
    },
    {
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        "time": "Sun Jul 18 12:21:01 2021 -0700"
      },
      "committer": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Sun Jul 18 12:21:01 2021 -0700"
      },
      "message": "adding ./signoff/tapeout.log\n"
    },
    {
      "commit": "0935d1c214ed3d11107a5a6e2e38dc3ae925db39",
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      },
      "committer": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Sun Jul 18 13:31:54 2021 +0000"
      },
      "message": "final gds \u0026 signoff results\n"
    },
    {
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      "author": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Sun Jul 18 13:13:22 2021 +0000"
      },
      "committer": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Sun Jul 18 13:13:22 2021 +0000"
      },
      "message": "final gds oasis\n"
    },
    {
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      "author": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Mon Jun 14 20:58:27 2021 -0600"
      },
      "committer": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Mon Jun 14 20:58:27 2021 -0600"
      },
      "message": "update README\n"
    },
    {
      "commit": "4300a9d0658cd67a5218825371ae2b1d1790f5f5",
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        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sun Jun 13 14:01:46 2021 -0600"
      },
      "committer": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sun Jun 13 14:01:46 2021 -0600"
      },
      "message": "adding .gds. This passes all the prechecks.\n"
    },
    {
      "commit": "4fb49018947775d20e67e5a0ebc126a1fa86543d",
      "tree": "69363760dfe528ca77ceaeab9e424ca123297951",
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      "author": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sun Jun 13 13:55:02 2021 -0600"
      },
      "committer": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sun Jun 13 13:55:02 2021 -0600"
      },
      "message": "top level LVS passes. There is a weird bug where xschem subckt ordering in cellA gets messed from the cell to the analog tb. But that\u0027s a xschem problem not the layout.\n"
    },
    {
      "commit": "4b7b1f91df2d6deed0b7f963b11191910a0ed975",
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        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sun Jun 13 13:04:18 2021 -0600"
      },
      "committer": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sun Jun 13 13:04:18 2021 -0600"
      },
      "message": "wrapper level routing complete. will try netgen with a newer version now for pin matching issues.\n"
    },
    {
      "commit": "077140914c32ced085a25d45c7d78da98892ac68",
      "tree": "54680d1cbec7c38bb2708c71e59a719a5fc6e258",
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      "author": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sun Jun 13 09:54:51 2021 -0600"
      },
      "committer": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sun Jun 13 09:54:51 2021 -0600"
      },
      "message": "Placed the sawgen cell and identified output pins. ready for final routing.\n"
    },
    {
      "commit": "e27065894debeb66723c1a029473003d876668db",
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      "author": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sun Jun 13 09:36:19 2021 -0600"
      },
      "committer": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sun Jun 13 09:36:19 2021 -0600"
      },
      "message": "replace diodes w/ FET and passes LVS if I replace VSUBS -\u003e vss\n"
    },
    {
      "commit": "46c1085576e72d2bf1dc6349044e114193921b45",
      "tree": "cb85e8d9df8673b6241519bdcc06265574340b77",
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      "author": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sat Jun 12 22:16:35 2021 -0600"
      },
      "committer": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sat Jun 12 22:16:35 2021 -0600"
      },
      "message": "Using diode connected fet instead of diodes to avoid buggy LVS problem. This works just as well. Need to redo layout next.\n"
    },
    {
      "commit": "f15016008f7220b7d4aa4484aa97666db1921100",
      "tree": "107002e599b700230c8312846137655c6be940ed",
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        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sat Jun 12 22:08:34 2021 -0600"
      },
      "committer": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sat Jun 12 22:08:34 2021 -0600"
      },
      "message": "This layout is good but fails LVS. Looks like there is a problem with the diode model and LVS.\n"
    },
    {
      "commit": "2924d3fc711280404188cef58e40696cf6e13f1a",
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      "parents": [
        "73bff3ebeae98fd213a4b8b0581fb9346490a83d"
      ],
      "author": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sat Jun 12 16:13:13 2021 -0600"
      },
      "committer": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sat Jun 12 16:13:13 2021 -0600"
      },
      "message": "sawgen: first cut at layout. could be done. need to LVS / hand inspect a little.\n"
    },
    {
      "commit": "73bff3ebeae98fd213a4b8b0581fb9346490a83d",
      "tree": "75b68feb22361d0cb48d27400dcdfb56a4d3183d",
      "parents": [
        "19f2936358c697dd77e995810c36fb6958ec9f24"
      ],
      "author": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sat Jun 12 15:03:30 2021 -0600"
      },
      "committer": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sat Jun 12 15:03:30 2021 -0600"
      },
      "message": "sawgen: got all the ports sorted out\n"
    },
    {
      "commit": "19f2936358c697dd77e995810c36fb6958ec9f24",
      "tree": "0332d298c5bb4ccaf73f9df9117d316db3669b7d",
      "parents": [
        "e66f60e80e2cca4e90d7b9bbaea5b51d4b18215e"
      ],
      "author": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sat Jun 12 13:44:26 2021 -0600"
      },
      "committer": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sat Jun 12 13:44:26 2021 -0600"
      },
      "message": "initial magic w/ cells pulled in\n"
    },
    {
      "commit": "e66f60e80e2cca4e90d7b9bbaea5b51d4b18215e",
      "tree": "718e89ddad3ab458662c5f7894e3b056f79c9ca9",
      "parents": [
        "23fa8cd90b60e8d5685e8e857095c0352bfab46a"
      ],
      "author": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sat Jun 12 13:29:56 2021 -0600"
      },
      "committer": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sat Jun 12 13:29:56 2021 -0600"
      },
      "message": "created a schematic cell and testbench for the sawgen\n"
    },
    {
      "commit": "23fa8cd90b60e8d5685e8e857095c0352bfab46a",
      "tree": "39cbace96baa95a2cacabd93e7370517c0f8e637",
      "parents": [
        "902d29b64bc30c74fd802c472df9644d939a9d83"
      ],
      "author": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sat Jun 12 11:41:01 2021 -0600"
      },
      "committer": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sat Jun 12 11:41:01 2021 -0600"
      },
      "message": "checkpoint: working on making this a cell and testbench\n"
    },
    {
      "commit": "902d29b64bc30c74fd802c472df9644d939a9d83",
      "tree": "3295f8b65a5ed408ed1d744a08cbda6f4ff2591b",
      "parents": [
        "eabdb81ee784a3913a673013d35eface9f06ccdc"
      ],
      "author": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sat Jun 12 11:25:11 2021 -0600"
      },
      "committer": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sat Jun 12 11:25:11 2021 -0600"
      },
      "message": "cosmetic change to resistor value label (reduced font size and updated to nominal value)\n"
    },
    {
      "commit": "eabdb81ee784a3913a673013d35eface9f06ccdc",
      "tree": "bc05ea251eb6582c997327c44ac0cc4131e2aea4",
      "parents": [
        "3f86e97696f26e364ee63711bd3ee2ad22851f6f"
      ],
      "author": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sat Jun 12 11:04:39 2021 -0600"
      },
      "committer": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sat Jun 12 11:04:39 2021 -0600"
      },
      "message": "This sawgen is good enough. Going to use offchip cap.\n"
    },
    {
      "commit": "3f86e97696f26e364ee63711bd3ee2ad22851f6f",
      "tree": "81e53f1552e3a2d86f0510a5c4f5b8730e8b6a1a",
      "parents": [
        "565ace7fafb1f8300804b97d7e2d5f1c8963f00e"
      ],
      "author": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Thu Jun 10 22:03:10 2021 -0600"
      },
      "committer": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Thu Jun 10 22:03:10 2021 -0600"
      },
      "message": "this \"works\" but uses 5000x vpp caps. Will try varactor caps and more step down current mirrors...\n"
    },
    {
      "commit": "565ace7fafb1f8300804b97d7e2d5f1c8963f00e",
      "tree": "d996ef48295b4d03bd619bba7eed5ba8a867eb18",
      "parents": [
        "48437aed0916cb783bb5f6d0fb0fa72998c65bd6"
      ],
      "author": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Wed Jun 09 21:36:50 2021 -0600"
      },
      "committer": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Wed Jun 09 21:36:50 2021 -0600"
      },
      "message": "added a working FET version of the sawgen. Need to replace the BJT current source with a FET version and translate over to sky130.\n"
    },
    {
      "commit": "48437aed0916cb783bb5f6d0fb0fa72998c65bd6",
      "tree": "b8b871639c5cf03931edc731b74bb02482c3b104",
      "parents": [
        "b59487705a09024fa915c3980b17435e4bddc505"
      ],
      "author": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Tue Jun 08 22:23:31 2021 -0600"
      },
      "committer": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Tue Jun 08 22:23:31 2021 -0600"
      },
      "message": "got a working bjt version of a saw generator (using 3904 and 3906 models). It isn\u0027t great but it \"works\"\n"
    },
    {
      "commit": "b59487705a09024fa915c3980b17435e4bddc505",
      "tree": "0406b508dce4e655a0697b7493625a5ba088e987",
      "parents": [
        "5371abcf65f1c8a5ccd87b27748c3eda2f527509"
      ],
      "author": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sun May 30 20:25:36 2021 -0600"
      },
      "committer": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sun May 30 20:25:36 2021 -0600"
      },
      "message": "add .gds\n"
    },
    {
      "commit": "5371abcf65f1c8a5ccd87b27748c3eda2f527509",
      "tree": "892a7080ff5aed4a7b9e9f42f53b3d77020bf7e5",
      "parents": [
        "b6939d7317c1afc76fff2c5173682e03b5a62a83"
      ],
      "author": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sun May 30 20:13:12 2021 -0600"
      },
      "committer": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sun May 30 20:13:12 2021 -0600"
      },
      "message": "add compressed gds\n"
    },
    {
      "commit": "b6939d7317c1afc76fff2c5173682e03b5a62a83",
      "tree": "7085ba2409a9ed74913f9391d0d3dba4bae1cc00",
      "parents": [
        "2726fff9028242f3b16a19a8aea1462f75356506"
      ],
      "author": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sun May 30 20:03:22 2021 -0600"
      },
      "committer": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sun May 30 20:03:22 2021 -0600"
      },
      "message": "removed unused spice files in netgen\n"
    },
    {
      "commit": "2726fff9028242f3b16a19a8aea1462f75356506",
      "tree": "15f7a1130e9060ea0190e8019cb22a03f9d5105e",
      "parents": [
        "b486a3bad1d726a406f1d9b4aabac5854a1430ba"
      ],
      "author": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sun May 30 20:01:34 2021 -0600"
      },
      "committer": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sun May 30 20:01:34 2021 -0600"
      },
      "message": "corrected DRC errors. This is DRC clean.\n"
    },
    {
      "commit": "b486a3bad1d726a406f1d9b4aabac5854a1430ba",
      "tree": "07a6f411c22619ebd968768b7411b9307608cb37",
      "parents": [
        "61afc05714db7eb571d6b35670fe5d9fad6cae2f"
      ],
      "author": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sat May 29 15:31:34 2021 -0600"
      },
      "committer": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sat May 29 15:31:34 2021 -0600"
      },
      "message": "needed to create the .gds manually with magic before running make run-precheck. now the precheck runs. I have a few DRC things to fix.\n"
    },
    {
      "commit": "61afc05714db7eb571d6b35670fe5d9fad6cae2f",
      "tree": "4670efc07be1f0947aeda51d727317f14e79280b",
      "parents": [
        "422aea5f1fea28bdae7cc43ee3eac287afb49834"
      ],
      "author": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Thu May 27 22:11:37 2021 -0600"
      },
      "committer": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Thu May 27 22:11:37 2021 -0600"
      },
      "message": "added CARAVEL_ROOT to the source.this\n"
    },
    {
      "commit": "422aea5f1fea28bdae7cc43ee3eac287afb49834",
      "tree": "9c557f84bdbdbfa32ac7025dd012bea049b4bd03",
      "parents": [
        "b6c1060ddc6fedcd398e76f7e940baa7f98cdf67"
      ],
      "author": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sun May 23 22:35:17 2021 -0600"
      },
      "committer": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sun May 23 22:35:17 2021 -0600"
      },
      "message": "added source.this to setup env\n"
    },
    {
      "commit": "b6c1060ddc6fedcd398e76f7e940baa7f98cdf67",
      "tree": "6c054756eb3e634d14fbd0537a255411f044d7f7",
      "parents": [
        "4464a60146417bbb747032a17e8f22bb6bc539b4"
      ],
      "author": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sun May 23 21:34:41 2021 -0600"
      },
      "committer": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sun May 23 21:34:41 2021 -0600"
      },
      "message": "layout complete and passes LVS. turn off parasitics: extract no capacitance, resistance, coupling. extract all.\n"
    },
    {
      "commit": "4464a60146417bbb747032a17e8f22bb6bc539b4",
      "tree": "68e341cd1c410b94caf3a1a6c8c33684af0e6c11",
      "parents": [
        "a4ef6cf56541ae7cf18c858e92d50bcd92b084d9"
      ],
      "author": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sun May 23 16:04:43 2021 -0600"
      },
      "committer": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sun May 23 16:04:43 2021 -0600"
      },
      "message": "added test resistor .mag\n"
    },
    {
      "commit": "a4ef6cf56541ae7cf18c858e92d50bcd92b084d9",
      "tree": "f42bc204f07464580c37914085b88c1de56574ad",
      "parents": [
        "b5dbdb2475045f6f237e685c4906bbb2aeebd513"
      ],
      "author": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sun May 23 16:00:16 2021 -0600"
      },
      "committer": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sun May 23 16:00:16 2021 -0600"
      },
      "message": "added a test resistor to help determin what the fabbed value will be\n"
    },
    {
      "commit": "b5dbdb2475045f6f237e685c4906bbb2aeebd513",
      "tree": "a478b5053a57e2880db80b83a8447af1d0aac416",
      "parents": [
        "49650f0dc8b121d40624f5950e5469a96c37ea5e"
      ],
      "author": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sat May 22 21:14:15 2021 -0600"
      },
      "committer": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sat May 22 21:14:15 2021 -0600"
      },
      "message": "cell passes LVS.\n"
    },
    {
      "commit": "49650f0dc8b121d40624f5950e5469a96c37ea5e",
      "tree": "b9e6fb89570ef57fbd4bbc1ea1e0a2bc00feb53b",
      "parents": [
        "26c027a3b6b249c1a0a57015c054df3ab1a26115"
      ],
      "author": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sat May 22 17:09:38 2021 -0600"
      },
      "committer": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sat May 22 17:09:38 2021 -0600"
      },
      "message": "progress on layout and ports\n"
    },
    {
      "commit": "26c027a3b6b249c1a0a57015c054df3ab1a26115",
      "tree": "6e5d9c6839d703383d29987ae1ea1583b19cfbd5",
      "parents": [
        "beb4f4251e280ef83e1d5ef5bce4ba4bb2e72360"
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      "author": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sat May 22 16:26:31 2021 -0600"
      },
      "committer": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Sat May 22 16:26:31 2021 -0600"
      },
      "message": "indexed ports correctly on the layout. subckt ports match schematic.\n"
    },
    {
      "commit": "beb4f4251e280ef83e1d5ef5bce4ba4bb2e72360",
      "tree": "5133cb9c594dd9c07562c850c1d4411c1620fed9",
      "parents": [
        "c879bef71d8434e5dc0f82294787a1552547ad6d"
      ],
      "author": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Wed May 19 22:30:59 2021 -0600"
      },
      "committer": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Wed May 19 22:30:59 2021 -0600"
      },
      "message": "lvs runs now (needed the testbech on the schematic side to get the includes). They don\u0027t match.\n"
    },
    {
      "commit": "c879bef71d8434e5dc0f82294787a1552547ad6d",
      "tree": "3c3aae2d50a30f42a4fd46110aa1332a0abeec8e",
      "parents": [
        "727bf6f88939be0327c3d950f5c8a31f067e8bc8"
      ],
      "author": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Wed May 19 22:07:19 2021 -0600"
      },
      "committer": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Wed May 19 22:07:19 2021 -0600"
      },
      "message": "made a layout and named some ports (incorrectly) but extract then ext2spice produces a subckt. lvs isn\u0027t running correctly (can\u0027t detect the cell in the xschem netlist for some reason)\n"
    },
    {
      "commit": "727bf6f88939be0327c3d950f5c8a31f067e8bc8",
      "tree": "7c8c479667417dc2cceb0711fd8fa571bb50a10f",
      "parents": [
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      ],
      "author": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Wed May 19 20:37:44 2021 -0600"
      },
      "committer": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Wed May 19 20:37:44 2021 -0600"
      },
      "message": "pull the test circuit out into a subckt and make a testbench for it. getting ready to layout and lvs just the cell.\n"
    },
    {
      "commit": "e1877c28d8f1cded37415042c3a15430bda0c09b",
      "tree": "ccada590228b26a5fa76845fd4810ee5708de2ad",
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      "author": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Mon May 17 21:37:39 2021 -0600"
      },
      "committer": {
        "name": "Mariano Alvira",
        "email": "mar@devl.org",
        "time": "Mon May 17 21:37:39 2021 -0600"
      },
      "message": "added cellA: a simple common source amplifier w/ 9kOhm resistor load to get started. Gain about 100, rolls off between 1 and 10 GHz.\n"
    },
    {
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        "time": "Sat May 08 18:24:21 2021 +0000"
      },
      "committer": {
        "name": "Git bot",
        "email": "bot@noreply.github.com",
        "time": "Sat May 08 18:24:21 2021 +0000"
      },
      "message": "Auto updated submodule references\n"
    },
    {
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      "author": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Sat May 08 13:47:45 2021 -0400"
      },
      "committer": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Sat May 08 13:47:45 2021 -0400"
      },
      "message": "Updated the documentation to include a description of the power-on-reset\ncircuit and the completed user project example.\n"
    },
    {
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        "time": "Sat May 08 18:43:17 2021 +0200"
      },
      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Sat May 08 18:43:17 2021 +0200"
      },
      "message": "Update index.rst"
    },
    {
      "commit": "520ff4ac3cd703accd51b465ab484a7aa15f6a0e",
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        "email": "manarabdelatty@aucegypt.edu",
        "time": "Sat May 08 18:39:47 2021 +0200"
      },
      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Sat May 08 18:39:47 2021 +0200"
      },
      "message": "Update index.rst"
    },
    {
      "commit": "a119592c1a186217c84b939b5698462870cc4f67",
      "tree": "e04aefef9c029be82ac24022b6ad7663f6845d86",
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        "time": "Sat May 08 18:38:16 2021 +0200"
      },
      "committer": {
        "name": "GitHub",
        "email": "noreply@github.com",
        "time": "Sat May 08 18:38:16 2021 +0200"
      },
      "message": "Update index.rst"
    },
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        "time": "Wed Apr 28 14:08:25 2021 -0400"
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        "time": "Wed Apr 28 14:05:41 2021 -0400"
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      "message": "Preliminary work on the analog user project example.  Added verilog RTL and\ntestbench.  The design passes the testbench.\n"
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}