)]}'
{
  "commit": "727bf6f88939be0327c3d950f5c8a31f067e8bc8",
  "tree": "7c8c479667417dc2cceb0711fd8fa571bb50a10f",
  "parents": [
    "e1877c28d8f1cded37415042c3a15430bda0c09b"
  ],
  "author": {
    "name": "Mariano Alvira",
    "email": "mar@devl.org",
    "time": "Wed May 19 20:37:44 2021 -0600"
  },
  "committer": {
    "name": "Mariano Alvira",
    "email": "mar@devl.org",
    "time": "Wed May 19 20:37:44 2021 -0600"
  },
  "message": "pull the test circuit out into a subckt and make a testbench for it. getting ready to layout and lvs just the cell.\n",
  "tree_diff": [
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      "type": "modify",
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      "old_mode": 33188,
      "old_path": "xschem/cellA.sch",
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      "new_mode": 33188,
      "new_path": "xschem/cellA.sch"
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}