v {xschem version=2.9.9 file_version=1.2 }
G {}
K {type=subcircuit
format="@name @pinlist @symname"
verilog_primitive=true
template="name=x1"
}
V {}
S {}
E {}
L 4 -130 -30 130 -30 {}
L 4 -130 30 130 30 {}
L 4 -130 -30 -130 30 {}
L 4 130 -30 130 30 {}
L 4 -150 -20 -130 -20 {}
L 7 130 -20 150 -20 {}
L 7 130 0 150 0 {}
L 7 130 20 150 20 {}
B 5 147.5 -22.5 152.5 -17.5 {name=DRAIN dir=inout }
B 5 -152.5 -22.5 -147.5 -17.5 {name=GATE dir=in }
B 5 147.5 -2.5 152.5 2.5 {name=VGND dir=inout }
B 5 147.5 17.5 152.5 22.5 {name=SOURCE dir=inout }
T {nFETLarge} -117 -6 0 0 0.3 0.3 {}
T {@name} 135 -42 0 0 0.2 0.2 {}
T {DRAIN} 125 -24 0 1 0.2 0.2 {}
T {GATE} -125 -24 0 0 0.2 0.2 {}
T {VGND} 125 -4 0 1 0.2 0.2 {}
T {SOURCE} 125 16 0 1 0.2 0.2 {}