/** Copyright 2020 The Hilas PDK Authors
 * 
 * This file is part of HILAS.
 * 
 * HILAS is free software: you can redistribute it and/or modify
 * it under the terms of the GNU Lesser General Public License as published by
 * the Free Software Foundation, version 3 of the License.
 * 
 * HILAS is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU Lesser General Public License for more details.
 * 
 * You should have received a copy of the GNU Lesser General Public License
 * along with HILAS.  If not, see <https://www.gnu.org/licenses/>.
 * 
 * Licensed under the Lesser General Public License, Version 3.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 * 
 * https://www.gnu.org/licenses/lgpl-3.0.en.html
 * 
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 * 
 * SPDX-License-Identifier: LGPL-3.0
 * 
 * 
 */


`define USE_POWER_PINS 1

`ifndef SKY130_HILAS_VINJDIODEPROTECT01
`define SKY130_HILAS_VINJDIODEPROTECT01

/**
 * sky130_hilas_VinjDiodeProtect01: protective ESD diode for VINJ line
 *
 * Verilog wrapper for sky130_hilas_VinjDiodeProtect01.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_VinjDiodeProtect01 (
    VINJ,
    INPUT,
    VGND,
    VNB,
    VPB
);
        inout VINJ;
        inout INPUT;
        inout VGND;
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_VinjDiodeProtect01 (
    VINJ,
    INPUT
);
        inout VINJ;
        inout INPUT;
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_VINJDIODEPROTECT01


//--------EOF---------

`ifndef SKY130_HILAS_TGATESINGLE01PART2
`define SKY130_HILAS_TGATESINGLE01PART2

/**
 * sky130_hilas_TgateSingle01Part2: None
 *
 * Verilog wrapper for sky130_hilas_TgateSingle01Part2.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_TgateSingle01Part2 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_TgateSingle01Part2 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_TGATESINGLE01PART2


//--------EOF---------

`ifndef SKY130_HILAS_ALL
`define SKY130_HILAS_ALL

/**
 * sky130_hilas_all: A design which contains all cells (?)
 *
 * Verilog wrapper for sky130_hilas_all.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_all (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_all (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_ALL


//--------EOF---------

`ifndef SKY130_HILAS_NFET03A
`define SKY130_HILAS_NFET03A

/**
 * sky130_hilas_nFET03a: None
 *
 * Verilog wrapper for sky130_hilas_nFET03a.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_nFET03a (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_nFET03a (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_NFET03A


//--------EOF---------

`ifndef SKY130_HILAS_DAC6TRANSISTORSTACK01
`define SKY130_HILAS_DAC6TRANSISTORSTACK01

/**
 * sky130_hilas_DAC6TransistorStack01: None
 *
 * Verilog wrapper for sky130_hilas_DAC6TransistorStack01.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_DAC6TransistorStack01 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_DAC6TransistorStack01 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_DAC6TRANSISTORSTACK01


//--------EOF---------

`ifndef SKY130_HILAS_TA2CELL_1FG_STRONG
`define SKY130_HILAS_TA2CELL_1FG_STRONG

/**
 * sky130_hilas_TA2Cell_1FG_Strong: Two transimpedance amps with one (of two) amplifiers using floating-gate inputs. FG amplifier with normal linear range.
 *
 * Verilog wrapper for sky130_hilas_TA2Cell_1FG_Strong.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_TA2Cell_1FG_Strong (
    VTUN,
    PROG,
    GATE1,
    VIN11,
    VINJ,
    VIN22,
    VIN21,
    OUTPUT2,
    OUTPUT1,
    GATESEL1,
    GATESEL2,
    DRAIN1,
    DRAIN2,
    VIN12,
    GATE2,
    RUN,
    VPWR,
    VGND,
    VNB,
    VPB
);
        inout VTUN;
        inout PROG;
        inout GATE1;
        inout VIN11;
        inout VINJ;
        inout VIN22;
        inout VIN21;
        inout OUTPUT2;
        inout OUTPUT1;
        inout GATESEL1;
        inout GATESEL2;
        inout DRAIN1;
        inout DRAIN2;
        inout VIN12;
        inout GATE2;
        inout RUN;
        inout VPWR;
        inout VGND;
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_TA2Cell_1FG_Strong (
    VTUN,
    PROG,
    GATE1,
    VIN11,
    VINJ,
    VIN22,
    VIN21,
    OUTPUT2,
    OUTPUT1,
    GATESEL1,
    GATESEL2,
    DRAIN1,
    DRAIN2,
    VIN12,
    GATE2,
    RUN
);
        inout VTUN;
        inout PROG;
        inout GATE1;
        inout VIN11;
        inout VINJ;
        inout VIN22;
        inout VIN21;
        inout OUTPUT2;
        inout OUTPUT1;
        inout GATESEL1;
        inout GATESEL2;
        inout DRAIN1;
        inout DRAIN2;
        inout VIN12;
        inout GATE2;
        inout RUN;
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_TA2CELL_1FG_STRONG


//--------EOF---------

`ifndef SKY130_HILAS_WTA4STAGE01
`define SKY130_HILAS_WTA4STAGE01

/**
 * sky130_hilas_WTA4stage01: single-element of WTA circuit
 *
 * Verilog wrapper for sky130_hilas_WTA4stage01.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_WTA4stage01 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_WTA4stage01 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_WTA4STAGE01


//--------EOF---------

`ifndef SKY130_HILAS_PFETMED
`define SKY130_HILAS_PFETMED

/**
 * sky130_hilas_pFETmed: Medium-sized (W/L=10) pFET transistor
 *
 * Verilog wrapper for sky130_hilas_pFETmed.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_pFETmed (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_pFETmed (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_PFETMED


//--------EOF---------

`ifndef SKY130_HILAS_CAPACITORSIZE02
`define SKY130_HILAS_CAPACITORSIZE02

/**
 * sky130_hilas_capacitorSize02: mid-small cap
 *
 * Verilog wrapper for sky130_hilas_capacitorSize02.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_capacitorSize02 (
    CAPTERM02,
    CAPTERM01,
    VNB,
    VPB
);
        inout CAPTERM02;
        inout CAPTERM01;
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_capacitorSize02 (
    CAPTERM02,
    CAPTERM01
);
        inout CAPTERM02;
        inout CAPTERM01;
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_CAPACITORSIZE02


//--------EOF---------

`ifndef SKY130_HILAS_SWC4X2CELLOVERLAP
`define SKY130_HILAS_SWC4X2CELLOVERLAP

/**
 * sky130_hilas_swc4x2cellOverlap: Core switch cell, built with overlap capacitor
 *
 * Verilog wrapper for sky130_hilas_swc4x2cellOverlap.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_swc4x2cellOverlap (
    VERT1,
    HORIZ1,
    DRAIN1,
    HORIZ2,
    DRAIN2,
    DRAIN3,
    HORIZ3,
    HORIZ4,
    DRAIN4,
    VINJ,
    GATESELECT1,
    VERT2,
    GATESELECT2,
    GATE2,
    GATE1,
    VTUN,
    VNB,
    VPB
);
        inout VERT1;
        inout HORIZ1;
        inout DRAIN1;
        inout HORIZ2;
        inout DRAIN2;
        inout DRAIN3;
        inout HORIZ3;
        inout HORIZ4;
        inout DRAIN4;
        inout VINJ;
        inout GATESELECT1;
        inout VERT2;
        inout GATESELECT2;
        inout GATE2;
        inout GATE1;
        inout VTUN;
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_swc4x2cellOverlap (
    VERT1,
    HORIZ1,
    DRAIN1,
    HORIZ2,
    DRAIN2,
    DRAIN3,
    HORIZ3,
    HORIZ4,
    DRAIN4,
    VINJ,
    GATESELECT1,
    VERT2,
    GATESELECT2,
    GATE2,
    GATE1,
    VTUN
);
        inout VERT1;
        inout HORIZ1;
        inout DRAIN1;
        inout HORIZ2;
        inout DRAIN2;
        inout DRAIN3;
        inout HORIZ3;
        inout HORIZ4;
        inout DRAIN4;
        inout VINJ;
        inout GATESELECT1;
        inout VERT2;
        inout GATESELECT2;
        inout GATE2;
        inout GATE1;
        inout VTUN;
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_SWC4X2CELLOVERLAP


//--------EOF---------

`ifndef SKY130_HILAS_POLY2LI
`define SKY130_HILAS_POLY2LI

/**
 * sky130_hilas_poly2li: polysilicon layer to li contact
 *
 * Verilog wrapper for sky130_hilas_poly2li.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_poly2li (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_poly2li (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_POLY2LI


//--------EOF---------

`ifndef SKY130_HILAS_DUALTACORE01
`define SKY130_HILAS_DUALTACORE01

/**
 * sky130_hilas_DualTACore01: None
 *
 * Verilog wrapper for sky130_hilas_DualTACore01.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_DualTACore01 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_DualTACore01 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_DUALTACORE01


//--------EOF---------

`ifndef SKY130_HILAS_TGATEVINJ01
`define SKY130_HILAS_TGATEVINJ01

/**
 * sky130_hilas_TgateVinj01: None
 *
 * Verilog wrapper for sky130_hilas_TgateVinj01.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_TgateVinj01 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_TgateVinj01 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_TGATEVINJ01


//--------EOF---------

`ifndef USER_ANALOG_PROJECT_WRAPPER
`define USER_ANALOG_PROJECT_WRAPPER

/**
 * user_analog_project_wrapper: 
 *
 * Verilog wrapper for user_analog_project_wrapper.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module user_analog_project_wrapper (
    gpio_analog[0],
    gpio_analog[10],
    gpio_analog[11],
    gpio_analog[12],
    gpio_analog[13],
    gpio_analog[14],
    gpio_analog[15],
    gpio_analog[16],
    gpio_analog[17],
    gpio_analog[1],
    gpio_analog[2],
    gpio_analog[3],
    gpio_analog[4],
    gpio_analog[5],
    gpio_analog[6],
    gpio_analog[7],
    gpio_analog[8],
    gpio_analog[9],
    gpio_noesd[0],
    gpio_noesd[10],
    gpio_noesd[11],
    gpio_noesd[12],
    gpio_noesd[13],
    gpio_noesd[14],
    gpio_noesd[15],
    gpio_noesd[16],
    gpio_noesd[17],
    gpio_noesd[1],
    gpio_noesd[2],
    gpio_noesd[3],
    gpio_noesd[4],
    gpio_noesd[5],
    gpio_noesd[6],
    gpio_noesd[7],
    gpio_noesd[8],
    gpio_noesd[9],
    io_analog[0],
    io_analog[10],
    io_analog[1],
    io_analog[2],
    io_analog[3],
    io_analog[4],
    io_analog[5],
    io_analog[6],
    io_analog[7],
    io_analog[8],
    io_analog[9],
    io_clamp_high[0],
    io_clamp_high[1],
    io_clamp_high[2],
    io_clamp_low[0],
    io_clamp_low[1],
    io_clamp_low[2],
    io_in[0],
    io_in[10],
    io_in[11],
    io_in[12],
    io_in[13],
    io_in[14],
    io_in[15],
    io_in[16],
    io_in[17],
    io_in[18],
    io_in[19],
    io_in[1],
    io_in[20],
    io_in[21],
    io_in[22],
    io_in[23],
    io_in[24],
    io_in[25],
    io_in[26],
    io_in[2],
    io_in[3],
    io_in[4],
    io_in[5],
    io_in[6],
    io_in[7],
    io_in[8],
    io_in[9],
    io_in_3v3[0],
    io_in_3v3[10],
    io_in_3v3[11],
    io_in_3v3[12],
    io_in_3v3[13],
    io_in_3v3[14],
    io_in_3v3[15],
    io_in_3v3[16],
    io_in_3v3[17],
    io_in_3v3[18],
    io_in_3v3[19],
    io_in_3v3[1],
    io_in_3v3[20],
    io_in_3v3[21],
    io_in_3v3[22],
    io_in_3v3[23],
    io_in_3v3[24],
    io_in_3v3[25],
    io_in_3v3[26],
    io_in_3v3[2],
    io_in_3v3[3],
    io_in_3v3[4],
    io_in_3v3[5],
    io_in_3v3[6],
    io_in_3v3[7],
    io_in_3v3[8],
    io_in_3v3[9],
    io_oeb[0],
    io_oeb[10],
    io_oeb[11],
    io_oeb[12],
    io_oeb[13],
    io_oeb[14],
    io_oeb[15],
    io_oeb[16],
    io_oeb[17],
    io_oeb[18],
    io_oeb[19],
    io_oeb[1],
    io_oeb[20],
    io_oeb[21],
    io_oeb[22],
    io_oeb[23],
    io_oeb[24],
    io_oeb[25],
    io_oeb[26],
    io_oeb[2],
    io_oeb[3],
    io_oeb[4],
    io_oeb[5],
    io_oeb[6],
    io_oeb[7],
    io_oeb[8],
    io_oeb[9],
    io_out[0],
    io_out[10],
    io_out[11],
    io_out[12],
    io_out[13],
    io_out[14],
    io_out[15],
    io_out[16],
    io_out[17],
    io_out[18],
    io_out[19],
    io_out[1],
    io_out[20],
    io_out[21],
    io_out[22],
    io_out[23],
    io_out[24],
    io_out[25],
    io_out[26],
    io_out[2],
    io_out[3],
    io_out[4],
    io_out[5],
    io_out[6],
    io_out[7],
    io_out[8],
    io_out[9],
    la_data_in[0],
    la_data_in[100],
    la_data_in[101],
    la_data_in[102],
    la_data_in[103],
    la_data_in[104],
    la_data_in[105],
    la_data_in[106],
    la_data_in[107],
    la_data_in[108],
    la_data_in[109],
    la_data_in[10],
    la_data_in[110],
    la_data_in[111],
    la_data_in[112],
    la_data_in[113],
    la_data_in[114],
    la_data_in[115],
    la_data_in[116],
    la_data_in[117],
    la_data_in[118],
    la_data_in[119],
    la_data_in[11],
    la_data_in[120],
    la_data_in[121],
    la_data_in[122],
    la_data_in[123],
    la_data_in[124],
    la_data_in[125],
    la_data_in[126],
    la_data_in[127],
    la_data_in[12],
    la_data_in[13],
    la_data_in[14],
    la_data_in[15],
    la_data_in[16],
    la_data_in[17],
    la_data_in[18],
    la_data_in[19],
    la_data_in[1],
    la_data_in[20],
    la_data_in[21],
    la_data_in[22],
    la_data_in[23],
    la_data_in[24],
    la_data_in[25],
    la_data_in[26],
    la_data_in[27],
    la_data_in[28],
    la_data_in[29],
    la_data_in[2],
    la_data_in[30],
    la_data_in[31],
    la_data_in[32],
    la_data_in[33],
    la_data_in[34],
    la_data_in[35],
    la_data_in[36],
    la_data_in[37],
    la_data_in[38],
    la_data_in[39],
    la_data_in[3],
    la_data_in[40],
    la_data_in[41],
    la_data_in[42],
    la_data_in[43],
    la_data_in[44],
    la_data_in[45],
    la_data_in[46],
    la_data_in[47],
    la_data_in[48],
    la_data_in[49],
    la_data_in[4],
    la_data_in[50],
    la_data_in[51],
    la_data_in[52],
    la_data_in[53],
    la_data_in[54],
    la_data_in[55],
    la_data_in[56],
    la_data_in[57],
    la_data_in[58],
    la_data_in[59],
    la_data_in[5],
    la_data_in[60],
    la_data_in[61],
    la_data_in[62],
    la_data_in[63],
    la_data_in[64],
    la_data_in[65],
    la_data_in[66],
    la_data_in[67],
    la_data_in[68],
    la_data_in[69],
    la_data_in[6],
    la_data_in[70],
    la_data_in[71],
    la_data_in[72],
    la_data_in[73],
    la_data_in[74],
    la_data_in[75],
    la_data_in[76],
    la_data_in[77],
    la_data_in[78],
    la_data_in[79],
    la_data_in[7],
    la_data_in[80],
    la_data_in[81],
    la_data_in[82],
    la_data_in[83],
    la_data_in[84],
    la_data_in[85],
    la_data_in[86],
    la_data_in[87],
    la_data_in[88],
    la_data_in[89],
    la_data_in[8],
    la_data_in[90],
    la_data_in[91],
    la_data_in[92],
    la_data_in[93],
    la_data_in[94],
    la_data_in[95],
    la_data_in[96],
    la_data_in[97],
    la_data_in[98],
    la_data_in[99],
    la_data_in[9],
    la_data_out[0],
    la_data_out[100],
    la_data_out[101],
    la_data_out[102],
    la_data_out[103],
    la_data_out[104],
    la_data_out[105],
    la_data_out[106],
    la_data_out[107],
    la_data_out[108],
    la_data_out[109],
    la_data_out[10],
    la_data_out[110],
    la_data_out[111],
    la_data_out[112],
    la_data_out[113],
    la_data_out[114],
    la_data_out[115],
    la_data_out[116],
    la_data_out[117],
    la_data_out[118],
    la_data_out[119],
    la_data_out[11],
    la_data_out[120],
    la_data_out[121],
    la_data_out[122],
    la_data_out[123],
    la_data_out[124],
    la_data_out[125],
    la_data_out[126],
    la_data_out[127],
    la_data_out[12],
    la_data_out[13],
    la_data_out[14],
    la_data_out[15],
    la_data_out[16],
    la_data_out[17],
    la_data_out[18],
    la_data_out[19],
    la_data_out[1],
    la_data_out[20],
    la_data_out[21],
    la_data_out[22],
    la_data_out[23],
    la_data_out[24],
    la_data_out[25],
    la_data_out[26],
    la_data_out[27],
    la_data_out[28],
    la_data_out[29],
    la_data_out[2],
    la_data_out[30],
    la_data_out[31],
    la_data_out[32],
    la_data_out[33],
    la_data_out[34],
    la_data_out[35],
    la_data_out[36],
    la_data_out[37],
    la_data_out[38],
    la_data_out[39],
    la_data_out[3],
    la_data_out[40],
    la_data_out[41],
    la_data_out[42],
    la_data_out[43],
    la_data_out[44],
    la_data_out[45],
    la_data_out[46],
    la_data_out[47],
    la_data_out[48],
    la_data_out[49],
    la_data_out[4],
    la_data_out[50],
    la_data_out[51],
    la_data_out[52],
    la_data_out[53],
    la_data_out[54],
    la_data_out[55],
    la_data_out[56],
    la_data_out[57],
    la_data_out[58],
    la_data_out[59],
    la_data_out[5],
    la_data_out[60],
    la_data_out[61],
    la_data_out[62],
    la_data_out[63],
    la_data_out[64],
    la_data_out[65],
    la_data_out[66],
    la_data_out[67],
    la_data_out[68],
    la_data_out[69],
    la_data_out[6],
    la_data_out[70],
    la_data_out[71],
    la_data_out[72],
    la_data_out[73],
    la_data_out[74],
    la_data_out[75],
    la_data_out[76],
    la_data_out[77],
    la_data_out[78],
    la_data_out[79],
    la_data_out[7],
    la_data_out[80],
    la_data_out[81],
    la_data_out[82],
    la_data_out[83],
    la_data_out[84],
    la_data_out[85],
    la_data_out[86],
    la_data_out[87],
    la_data_out[88],
    la_data_out[89],
    la_data_out[8],
    la_data_out[90],
    la_data_out[91],
    la_data_out[92],
    la_data_out[93],
    la_data_out[94],
    la_data_out[95],
    la_data_out[96],
    la_data_out[97],
    la_data_out[98],
    la_data_out[99],
    la_data_out[9],
    la_oenb[0],
    la_oenb[100],
    la_oenb[101],
    la_oenb[102],
    la_oenb[103],
    la_oenb[104],
    la_oenb[105],
    la_oenb[106],
    la_oenb[107],
    la_oenb[108],
    la_oenb[109],
    la_oenb[10],
    la_oenb[110],
    la_oenb[111],
    la_oenb[112],
    la_oenb[113],
    la_oenb[114],
    la_oenb[115],
    la_oenb[116],
    la_oenb[117],
    la_oenb[118],
    la_oenb[119],
    la_oenb[11],
    la_oenb[120],
    la_oenb[121],
    la_oenb[122],
    la_oenb[123],
    la_oenb[124],
    la_oenb[125],
    la_oenb[126],
    la_oenb[127],
    la_oenb[12],
    la_oenb[13],
    la_oenb[14],
    la_oenb[15],
    la_oenb[16],
    la_oenb[17],
    la_oenb[18],
    la_oenb[19],
    la_oenb[1],
    la_oenb[20],
    la_oenb[21],
    la_oenb[22],
    la_oenb[23],
    la_oenb[24],
    la_oenb[25],
    la_oenb[26],
    la_oenb[27],
    la_oenb[28],
    la_oenb[29],
    la_oenb[2],
    la_oenb[30],
    la_oenb[31],
    la_oenb[32],
    la_oenb[33],
    la_oenb[34],
    la_oenb[35],
    la_oenb[36],
    la_oenb[37],
    la_oenb[38],
    la_oenb[39],
    la_oenb[3],
    la_oenb[40],
    la_oenb[41],
    la_oenb[42],
    la_oenb[43],
    la_oenb[44],
    la_oenb[45],
    la_oenb[46],
    la_oenb[47],
    la_oenb[48],
    la_oenb[49],
    la_oenb[4],
    la_oenb[50],
    la_oenb[51],
    la_oenb[52],
    la_oenb[53],
    la_oenb[54],
    la_oenb[55],
    la_oenb[56],
    la_oenb[57],
    la_oenb[58],
    la_oenb[59],
    la_oenb[5],
    la_oenb[60],
    la_oenb[61],
    la_oenb[62],
    la_oenb[63],
    la_oenb[64],
    la_oenb[65],
    la_oenb[66],
    la_oenb[67],
    la_oenb[68],
    la_oenb[69],
    la_oenb[6],
    la_oenb[70],
    la_oenb[71],
    la_oenb[72],
    la_oenb[73],
    la_oenb[74],
    la_oenb[75],
    la_oenb[76],
    la_oenb[77],
    la_oenb[78],
    la_oenb[79],
    la_oenb[7],
    la_oenb[80],
    la_oenb[81],
    la_oenb[82],
    la_oenb[83],
    la_oenb[84],
    la_oenb[85],
    la_oenb[86],
    la_oenb[87],
    la_oenb[88],
    la_oenb[89],
    la_oenb[8],
    la_oenb[90],
    la_oenb[91],
    la_oenb[92],
    la_oenb[93],
    la_oenb[94],
    la_oenb[95],
    la_oenb[96],
    la_oenb[97],
    la_oenb[98],
    la_oenb[99],
    la_oenb[9],
    user_clock2,
    user_irq[0],
    user_irq[1],
    user_irq[2],
    vccd1,
    vccd2,
    vdda1,
    vdda2,
    vssa1,
    vssa2,
    vssd1,
    vssd2,
    wb_clk_i,
    wb_rst_i,
    wbs_ack_o,
    wbs_adr_i[0],
    wbs_adr_i[10],
    wbs_adr_i[11],
    wbs_adr_i[12],
    wbs_adr_i[13],
    wbs_adr_i[14],
    wbs_adr_i[15],
    wbs_adr_i[16],
    wbs_adr_i[17],
    wbs_adr_i[18],
    wbs_adr_i[19],
    wbs_adr_i[1],
    wbs_adr_i[20],
    wbs_adr_i[21],
    wbs_adr_i[22],
    wbs_adr_i[23],
    wbs_adr_i[24],
    wbs_adr_i[25],
    wbs_adr_i[26],
    wbs_adr_i[27],
    wbs_adr_i[28],
    wbs_adr_i[29],
    wbs_adr_i[2],
    wbs_adr_i[30],
    wbs_adr_i[31],
    wbs_adr_i[3],
    wbs_adr_i[4],
    wbs_adr_i[5],
    wbs_adr_i[6],
    wbs_adr_i[7],
    wbs_adr_i[8],
    wbs_adr_i[9],
    wbs_cyc_i,
    wbs_dat_i[0],
    wbs_dat_i[10],
    wbs_dat_i[11],
    wbs_dat_i[12],
    wbs_dat_i[13],
    wbs_dat_i[14],
    wbs_dat_i[15],
    wbs_dat_i[16],
    wbs_dat_i[17],
    wbs_dat_i[18],
    wbs_dat_i[19],
    wbs_dat_i[1],
    wbs_dat_i[20],
    wbs_dat_i[21],
    wbs_dat_i[22],
    wbs_dat_i[23],
    wbs_dat_i[24],
    wbs_dat_i[25],
    wbs_dat_i[26],
    wbs_dat_i[27],
    wbs_dat_i[28],
    wbs_dat_i[29],
    wbs_dat_i[2],
    wbs_dat_i[30],
    wbs_dat_i[31],
    wbs_dat_i[3],
    wbs_dat_i[4],
    wbs_dat_i[5],
    wbs_dat_i[6],
    wbs_dat_i[7],
    wbs_dat_i[8],
    wbs_dat_i[9],
    wbs_dat_o[0],
    wbs_dat_o[10],
    wbs_dat_o[11],
    wbs_dat_o[12],
    wbs_dat_o[13],
    wbs_dat_o[14],
    wbs_dat_o[15],
    wbs_dat_o[16],
    wbs_dat_o[17],
    wbs_dat_o[18],
    wbs_dat_o[19],
    wbs_dat_o[1],
    wbs_dat_o[20],
    wbs_dat_o[21],
    wbs_dat_o[22],
    wbs_dat_o[23],
    wbs_dat_o[24],
    wbs_dat_o[25],
    wbs_dat_o[26],
    wbs_dat_o[27],
    wbs_dat_o[28],
    wbs_dat_o[29],
    wbs_dat_o[2],
    wbs_dat_o[30],
    wbs_dat_o[31],
    wbs_dat_o[3],
    wbs_dat_o[4],
    wbs_dat_o[5],
    wbs_dat_o[6],
    wbs_dat_o[7],
    wbs_dat_o[8],
    wbs_dat_o[9],
    wbs_sel_i[0],
    wbs_sel_i[1],
    wbs_sel_i[2],
    wbs_sel_i[3],
    wbs_stb_i,
    wbs_we_i,
    VNB,
    VPB
);
        inout gpio_analog[0];
        inout gpio_analog[10];
        inout gpio_analog[11];
        inout gpio_analog[12];
        inout gpio_analog[13];
        inout gpio_analog[14];
        inout gpio_analog[15];
        inout gpio_analog[16];
        inout gpio_analog[17];
        inout gpio_analog[1];
        inout gpio_analog[2];
        inout gpio_analog[3];
        inout gpio_analog[4];
        inout gpio_analog[5];
        inout gpio_analog[6];
        inout gpio_analog[7];
        inout gpio_analog[8];
        inout gpio_analog[9];
        inout gpio_noesd[0];
        inout gpio_noesd[10];
        inout gpio_noesd[11];
        inout gpio_noesd[12];
        inout gpio_noesd[13];
        inout gpio_noesd[14];
        inout gpio_noesd[15];
        inout gpio_noesd[16];
        inout gpio_noesd[17];
        inout gpio_noesd[1];
        inout gpio_noesd[2];
        inout gpio_noesd[3];
        inout gpio_noesd[4];
        inout gpio_noesd[5];
        inout gpio_noesd[6];
        inout gpio_noesd[7];
        inout gpio_noesd[8];
        inout gpio_noesd[9];
        inout io_analog[0];
        inout io_analog[10];
        inout io_analog[1];
        inout io_analog[2];
        inout io_analog[3];
        inout io_analog[4];
        inout io_analog[5];
        inout io_analog[6];
        inout io_analog[7];
        inout io_analog[8];
        inout io_analog[9];
        inout io_clamp_high[0];
        inout io_clamp_high[1];
        inout io_clamp_high[2];
        inout io_clamp_low[0];
        inout io_clamp_low[1];
        inout io_clamp_low[2];
        inout io_in[0];
        inout io_in[10];
        inout io_in[11];
        inout io_in[12];
        inout io_in[13];
        inout io_in[14];
        inout io_in[15];
        inout io_in[16];
        inout io_in[17];
        inout io_in[18];
        inout io_in[19];
        inout io_in[1];
        inout io_in[20];
        inout io_in[21];
        inout io_in[22];
        inout io_in[23];
        inout io_in[24];
        inout io_in[25];
        inout io_in[26];
        inout io_in[2];
        inout io_in[3];
        inout io_in[4];
        inout io_in[5];
        inout io_in[6];
        inout io_in[7];
        inout io_in[8];
        inout io_in[9];
        inout io_in_3v3[0];
        inout io_in_3v3[10];
        inout io_in_3v3[11];
        inout io_in_3v3[12];
        inout io_in_3v3[13];
        inout io_in_3v3[14];
        inout io_in_3v3[15];
        inout io_in_3v3[16];
        inout io_in_3v3[17];
        inout io_in_3v3[18];
        inout io_in_3v3[19];
        inout io_in_3v3[1];
        inout io_in_3v3[20];
        inout io_in_3v3[21];
        inout io_in_3v3[22];
        inout io_in_3v3[23];
        inout io_in_3v3[24];
        inout io_in_3v3[25];
        inout io_in_3v3[26];
        inout io_in_3v3[2];
        inout io_in_3v3[3];
        inout io_in_3v3[4];
        inout io_in_3v3[5];
        inout io_in_3v3[6];
        inout io_in_3v3[7];
        inout io_in_3v3[8];
        inout io_in_3v3[9];
        inout io_oeb[0];
        inout io_oeb[10];
        inout io_oeb[11];
        inout io_oeb[12];
        inout io_oeb[13];
        inout io_oeb[14];
        inout io_oeb[15];
        inout io_oeb[16];
        inout io_oeb[17];
        inout io_oeb[18];
        inout io_oeb[19];
        inout io_oeb[1];
        inout io_oeb[20];
        inout io_oeb[21];
        inout io_oeb[22];
        inout io_oeb[23];
        inout io_oeb[24];
        inout io_oeb[25];
        inout io_oeb[26];
        inout io_oeb[2];
        inout io_oeb[3];
        inout io_oeb[4];
        inout io_oeb[5];
        inout io_oeb[6];
        inout io_oeb[7];
        inout io_oeb[8];
        inout io_oeb[9];
        inout io_out[0];
        inout io_out[10];
        inout io_out[11];
        inout io_out[12];
        inout io_out[13];
        inout io_out[14];
        inout io_out[15];
        inout io_out[16];
        inout io_out[17];
        inout io_out[18];
        inout io_out[19];
        inout io_out[1];
        inout io_out[20];
        inout io_out[21];
        inout io_out[22];
        inout io_out[23];
        inout io_out[24];
        inout io_out[25];
        inout io_out[26];
        inout io_out[2];
        inout io_out[3];
        inout io_out[4];
        inout io_out[5];
        inout io_out[6];
        inout io_out[7];
        inout io_out[8];
        inout io_out[9];
        inout la_data_in[0];
        inout la_data_in[100];
        inout la_data_in[101];
        inout la_data_in[102];
        inout la_data_in[103];
        inout la_data_in[104];
        inout la_data_in[105];
        inout la_data_in[106];
        inout la_data_in[107];
        inout la_data_in[108];
        inout la_data_in[109];
        inout la_data_in[10];
        inout la_data_in[110];
        inout la_data_in[111];
        inout la_data_in[112];
        inout la_data_in[113];
        inout la_data_in[114];
        inout la_data_in[115];
        inout la_data_in[116];
        inout la_data_in[117];
        inout la_data_in[118];
        inout la_data_in[119];
        inout la_data_in[11];
        inout la_data_in[120];
        inout la_data_in[121];
        inout la_data_in[122];
        inout la_data_in[123];
        inout la_data_in[124];
        inout la_data_in[125];
        inout la_data_in[126];
        inout la_data_in[127];
        inout la_data_in[12];
        inout la_data_in[13];
        inout la_data_in[14];
        inout la_data_in[15];
        inout la_data_in[16];
        inout la_data_in[17];
        inout la_data_in[18];
        inout la_data_in[19];
        inout la_data_in[1];
        inout la_data_in[20];
        inout la_data_in[21];
        inout la_data_in[22];
        inout la_data_in[23];
        inout la_data_in[24];
        inout la_data_in[25];
        inout la_data_in[26];
        inout la_data_in[27];
        inout la_data_in[28];
        inout la_data_in[29];
        inout la_data_in[2];
        inout la_data_in[30];
        inout la_data_in[31];
        inout la_data_in[32];
        inout la_data_in[33];
        inout la_data_in[34];
        inout la_data_in[35];
        inout la_data_in[36];
        inout la_data_in[37];
        inout la_data_in[38];
        inout la_data_in[39];
        inout la_data_in[3];
        inout la_data_in[40];
        inout la_data_in[41];
        inout la_data_in[42];
        inout la_data_in[43];
        inout la_data_in[44];
        inout la_data_in[45];
        inout la_data_in[46];
        inout la_data_in[47];
        inout la_data_in[48];
        inout la_data_in[49];
        inout la_data_in[4];
        inout la_data_in[50];
        inout la_data_in[51];
        inout la_data_in[52];
        inout la_data_in[53];
        inout la_data_in[54];
        inout la_data_in[55];
        inout la_data_in[56];
        inout la_data_in[57];
        inout la_data_in[58];
        inout la_data_in[59];
        inout la_data_in[5];
        inout la_data_in[60];
        inout la_data_in[61];
        inout la_data_in[62];
        inout la_data_in[63];
        inout la_data_in[64];
        inout la_data_in[65];
        inout la_data_in[66];
        inout la_data_in[67];
        inout la_data_in[68];
        inout la_data_in[69];
        inout la_data_in[6];
        inout la_data_in[70];
        inout la_data_in[71];
        inout la_data_in[72];
        inout la_data_in[73];
        inout la_data_in[74];
        inout la_data_in[75];
        inout la_data_in[76];
        inout la_data_in[77];
        inout la_data_in[78];
        inout la_data_in[79];
        inout la_data_in[7];
        inout la_data_in[80];
        inout la_data_in[81];
        inout la_data_in[82];
        inout la_data_in[83];
        inout la_data_in[84];
        inout la_data_in[85];
        inout la_data_in[86];
        inout la_data_in[87];
        inout la_data_in[88];
        inout la_data_in[89];
        inout la_data_in[8];
        inout la_data_in[90];
        inout la_data_in[91];
        inout la_data_in[92];
        inout la_data_in[93];
        inout la_data_in[94];
        inout la_data_in[95];
        inout la_data_in[96];
        inout la_data_in[97];
        inout la_data_in[98];
        inout la_data_in[99];
        inout la_data_in[9];
        inout la_data_out[0];
        inout la_data_out[100];
        inout la_data_out[101];
        inout la_data_out[102];
        inout la_data_out[103];
        inout la_data_out[104];
        inout la_data_out[105];
        inout la_data_out[106];
        inout la_data_out[107];
        inout la_data_out[108];
        inout la_data_out[109];
        inout la_data_out[10];
        inout la_data_out[110];
        inout la_data_out[111];
        inout la_data_out[112];
        inout la_data_out[113];
        inout la_data_out[114];
        inout la_data_out[115];
        inout la_data_out[116];
        inout la_data_out[117];
        inout la_data_out[118];
        inout la_data_out[119];
        inout la_data_out[11];
        inout la_data_out[120];
        inout la_data_out[121];
        inout la_data_out[122];
        inout la_data_out[123];
        inout la_data_out[124];
        inout la_data_out[125];
        inout la_data_out[126];
        inout la_data_out[127];
        inout la_data_out[12];
        inout la_data_out[13];
        inout la_data_out[14];
        inout la_data_out[15];
        inout la_data_out[16];
        inout la_data_out[17];
        inout la_data_out[18];
        inout la_data_out[19];
        inout la_data_out[1];
        inout la_data_out[20];
        inout la_data_out[21];
        inout la_data_out[22];
        inout la_data_out[23];
        inout la_data_out[24];
        inout la_data_out[25];
        inout la_data_out[26];
        inout la_data_out[27];
        inout la_data_out[28];
        inout la_data_out[29];
        inout la_data_out[2];
        inout la_data_out[30];
        inout la_data_out[31];
        inout la_data_out[32];
        inout la_data_out[33];
        inout la_data_out[34];
        inout la_data_out[35];
        inout la_data_out[36];
        inout la_data_out[37];
        inout la_data_out[38];
        inout la_data_out[39];
        inout la_data_out[3];
        inout la_data_out[40];
        inout la_data_out[41];
        inout la_data_out[42];
        inout la_data_out[43];
        inout la_data_out[44];
        inout la_data_out[45];
        inout la_data_out[46];
        inout la_data_out[47];
        inout la_data_out[48];
        inout la_data_out[49];
        inout la_data_out[4];
        inout la_data_out[50];
        inout la_data_out[51];
        inout la_data_out[52];
        inout la_data_out[53];
        inout la_data_out[54];
        inout la_data_out[55];
        inout la_data_out[56];
        inout la_data_out[57];
        inout la_data_out[58];
        inout la_data_out[59];
        inout la_data_out[5];
        inout la_data_out[60];
        inout la_data_out[61];
        inout la_data_out[62];
        inout la_data_out[63];
        inout la_data_out[64];
        inout la_data_out[65];
        inout la_data_out[66];
        inout la_data_out[67];
        inout la_data_out[68];
        inout la_data_out[69];
        inout la_data_out[6];
        inout la_data_out[70];
        inout la_data_out[71];
        inout la_data_out[72];
        inout la_data_out[73];
        inout la_data_out[74];
        inout la_data_out[75];
        inout la_data_out[76];
        inout la_data_out[77];
        inout la_data_out[78];
        inout la_data_out[79];
        inout la_data_out[7];
        inout la_data_out[80];
        inout la_data_out[81];
        inout la_data_out[82];
        inout la_data_out[83];
        inout la_data_out[84];
        inout la_data_out[85];
        inout la_data_out[86];
        inout la_data_out[87];
        inout la_data_out[88];
        inout la_data_out[89];
        inout la_data_out[8];
        inout la_data_out[90];
        inout la_data_out[91];
        inout la_data_out[92];
        inout la_data_out[93];
        inout la_data_out[94];
        inout la_data_out[95];
        inout la_data_out[96];
        inout la_data_out[97];
        inout la_data_out[98];
        inout la_data_out[99];
        inout la_data_out[9];
        inout la_oenb[0];
        inout la_oenb[100];
        inout la_oenb[101];
        inout la_oenb[102];
        inout la_oenb[103];
        inout la_oenb[104];
        inout la_oenb[105];
        inout la_oenb[106];
        inout la_oenb[107];
        inout la_oenb[108];
        inout la_oenb[109];
        inout la_oenb[10];
        inout la_oenb[110];
        inout la_oenb[111];
        inout la_oenb[112];
        inout la_oenb[113];
        inout la_oenb[114];
        inout la_oenb[115];
        inout la_oenb[116];
        inout la_oenb[117];
        inout la_oenb[118];
        inout la_oenb[119];
        inout la_oenb[11];
        inout la_oenb[120];
        inout la_oenb[121];
        inout la_oenb[122];
        inout la_oenb[123];
        inout la_oenb[124];
        inout la_oenb[125];
        inout la_oenb[126];
        inout la_oenb[127];
        inout la_oenb[12];
        inout la_oenb[13];
        inout la_oenb[14];
        inout la_oenb[15];
        inout la_oenb[16];
        inout la_oenb[17];
        inout la_oenb[18];
        inout la_oenb[19];
        inout la_oenb[1];
        inout la_oenb[20];
        inout la_oenb[21];
        inout la_oenb[22];
        inout la_oenb[23];
        inout la_oenb[24];
        inout la_oenb[25];
        inout la_oenb[26];
        inout la_oenb[27];
        inout la_oenb[28];
        inout la_oenb[29];
        inout la_oenb[2];
        inout la_oenb[30];
        inout la_oenb[31];
        inout la_oenb[32];
        inout la_oenb[33];
        inout la_oenb[34];
        inout la_oenb[35];
        inout la_oenb[36];
        inout la_oenb[37];
        inout la_oenb[38];
        inout la_oenb[39];
        inout la_oenb[3];
        inout la_oenb[40];
        inout la_oenb[41];
        inout la_oenb[42];
        inout la_oenb[43];
        inout la_oenb[44];
        inout la_oenb[45];
        inout la_oenb[46];
        inout la_oenb[47];
        inout la_oenb[48];
        inout la_oenb[49];
        inout la_oenb[4];
        inout la_oenb[50];
        inout la_oenb[51];
        inout la_oenb[52];
        inout la_oenb[53];
        inout la_oenb[54];
        inout la_oenb[55];
        inout la_oenb[56];
        inout la_oenb[57];
        inout la_oenb[58];
        inout la_oenb[59];
        inout la_oenb[5];
        inout la_oenb[60];
        inout la_oenb[61];
        inout la_oenb[62];
        inout la_oenb[63];
        inout la_oenb[64];
        inout la_oenb[65];
        inout la_oenb[66];
        inout la_oenb[67];
        inout la_oenb[68];
        inout la_oenb[69];
        inout la_oenb[6];
        inout la_oenb[70];
        inout la_oenb[71];
        inout la_oenb[72];
        inout la_oenb[73];
        inout la_oenb[74];
        inout la_oenb[75];
        inout la_oenb[76];
        inout la_oenb[77];
        inout la_oenb[78];
        inout la_oenb[79];
        inout la_oenb[7];
        inout la_oenb[80];
        inout la_oenb[81];
        inout la_oenb[82];
        inout la_oenb[83];
        inout la_oenb[84];
        inout la_oenb[85];
        inout la_oenb[86];
        inout la_oenb[87];
        inout la_oenb[88];
        inout la_oenb[89];
        inout la_oenb[8];
        inout la_oenb[90];
        inout la_oenb[91];
        inout la_oenb[92];
        inout la_oenb[93];
        inout la_oenb[94];
        inout la_oenb[95];
        inout la_oenb[96];
        inout la_oenb[97];
        inout la_oenb[98];
        inout la_oenb[99];
        inout la_oenb[9];
        inout user_clock2;
        inout user_irq[0];
        inout user_irq[1];
        inout user_irq[2];
        inout vccd1;
        inout vccd2;
        inout vdda1;
        inout vdda2;
        inout vssa1;
        inout vssa2;
        inout vssd1;
        inout vssd2;
        inout wb_clk_i;
        inout wb_rst_i;
        inout wbs_ack_o;
        inout wbs_adr_i[0];
        inout wbs_adr_i[10];
        inout wbs_adr_i[11];
        inout wbs_adr_i[12];
        inout wbs_adr_i[13];
        inout wbs_adr_i[14];
        inout wbs_adr_i[15];
        inout wbs_adr_i[16];
        inout wbs_adr_i[17];
        inout wbs_adr_i[18];
        inout wbs_adr_i[19];
        inout wbs_adr_i[1];
        inout wbs_adr_i[20];
        inout wbs_adr_i[21];
        inout wbs_adr_i[22];
        inout wbs_adr_i[23];
        inout wbs_adr_i[24];
        inout wbs_adr_i[25];
        inout wbs_adr_i[26];
        inout wbs_adr_i[27];
        inout wbs_adr_i[28];
        inout wbs_adr_i[29];
        inout wbs_adr_i[2];
        inout wbs_adr_i[30];
        inout wbs_adr_i[31];
        inout wbs_adr_i[3];
        inout wbs_adr_i[4];
        inout wbs_adr_i[5];
        inout wbs_adr_i[6];
        inout wbs_adr_i[7];
        inout wbs_adr_i[8];
        inout wbs_adr_i[9];
        inout wbs_cyc_i;
        inout wbs_dat_i[0];
        inout wbs_dat_i[10];
        inout wbs_dat_i[11];
        inout wbs_dat_i[12];
        inout wbs_dat_i[13];
        inout wbs_dat_i[14];
        inout wbs_dat_i[15];
        inout wbs_dat_i[16];
        inout wbs_dat_i[17];
        inout wbs_dat_i[18];
        inout wbs_dat_i[19];
        inout wbs_dat_i[1];
        inout wbs_dat_i[20];
        inout wbs_dat_i[21];
        inout wbs_dat_i[22];
        inout wbs_dat_i[23];
        inout wbs_dat_i[24];
        inout wbs_dat_i[25];
        inout wbs_dat_i[26];
        inout wbs_dat_i[27];
        inout wbs_dat_i[28];
        inout wbs_dat_i[29];
        inout wbs_dat_i[2];
        inout wbs_dat_i[30];
        inout wbs_dat_i[31];
        inout wbs_dat_i[3];
        inout wbs_dat_i[4];
        inout wbs_dat_i[5];
        inout wbs_dat_i[6];
        inout wbs_dat_i[7];
        inout wbs_dat_i[8];
        inout wbs_dat_i[9];
        inout wbs_dat_o[0];
        inout wbs_dat_o[10];
        inout wbs_dat_o[11];
        inout wbs_dat_o[12];
        inout wbs_dat_o[13];
        inout wbs_dat_o[14];
        inout wbs_dat_o[15];
        inout wbs_dat_o[16];
        inout wbs_dat_o[17];
        inout wbs_dat_o[18];
        inout wbs_dat_o[19];
        inout wbs_dat_o[1];
        inout wbs_dat_o[20];
        inout wbs_dat_o[21];
        inout wbs_dat_o[22];
        inout wbs_dat_o[23];
        inout wbs_dat_o[24];
        inout wbs_dat_o[25];
        inout wbs_dat_o[26];
        inout wbs_dat_o[27];
        inout wbs_dat_o[28];
        inout wbs_dat_o[29];
        inout wbs_dat_o[2];
        inout wbs_dat_o[30];
        inout wbs_dat_o[31];
        inout wbs_dat_o[3];
        inout wbs_dat_o[4];
        inout wbs_dat_o[5];
        inout wbs_dat_o[6];
        inout wbs_dat_o[7];
        inout wbs_dat_o[8];
        inout wbs_dat_o[9];
        inout wbs_sel_i[0];
        inout wbs_sel_i[1];
        inout wbs_sel_i[2];
        inout wbs_sel_i[3];
        inout wbs_stb_i;
        inout wbs_we_i;
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module user_analog_project_wrapper (
    gpio_analog[0],
    gpio_analog[10],
    gpio_analog[11],
    gpio_analog[12],
    gpio_analog[13],
    gpio_analog[14],
    gpio_analog[15],
    gpio_analog[16],
    gpio_analog[17],
    gpio_analog[1],
    gpio_analog[2],
    gpio_analog[3],
    gpio_analog[4],
    gpio_analog[5],
    gpio_analog[6],
    gpio_analog[7],
    gpio_analog[8],
    gpio_analog[9],
    gpio_noesd[0],
    gpio_noesd[10],
    gpio_noesd[11],
    gpio_noesd[12],
    gpio_noesd[13],
    gpio_noesd[14],
    gpio_noesd[15],
    gpio_noesd[16],
    gpio_noesd[17],
    gpio_noesd[1],
    gpio_noesd[2],
    gpio_noesd[3],
    gpio_noesd[4],
    gpio_noesd[5],
    gpio_noesd[6],
    gpio_noesd[7],
    gpio_noesd[8],
    gpio_noesd[9],
    io_analog[0],
    io_analog[10],
    io_analog[1],
    io_analog[2],
    io_analog[3],
    io_analog[4],
    io_analog[5],
    io_analog[6],
    io_analog[7],
    io_analog[8],
    io_analog[9],
    io_clamp_high[0],
    io_clamp_high[1],
    io_clamp_high[2],
    io_clamp_low[0],
    io_clamp_low[1],
    io_clamp_low[2],
    io_in[0],
    io_in[10],
    io_in[11],
    io_in[12],
    io_in[13],
    io_in[14],
    io_in[15],
    io_in[16],
    io_in[17],
    io_in[18],
    io_in[19],
    io_in[1],
    io_in[20],
    io_in[21],
    io_in[22],
    io_in[23],
    io_in[24],
    io_in[25],
    io_in[26],
    io_in[2],
    io_in[3],
    io_in[4],
    io_in[5],
    io_in[6],
    io_in[7],
    io_in[8],
    io_in[9],
    io_in_3v3[0],
    io_in_3v3[10],
    io_in_3v3[11],
    io_in_3v3[12],
    io_in_3v3[13],
    io_in_3v3[14],
    io_in_3v3[15],
    io_in_3v3[16],
    io_in_3v3[17],
    io_in_3v3[18],
    io_in_3v3[19],
    io_in_3v3[1],
    io_in_3v3[20],
    io_in_3v3[21],
    io_in_3v3[22],
    io_in_3v3[23],
    io_in_3v3[24],
    io_in_3v3[25],
    io_in_3v3[26],
    io_in_3v3[2],
    io_in_3v3[3],
    io_in_3v3[4],
    io_in_3v3[5],
    io_in_3v3[6],
    io_in_3v3[7],
    io_in_3v3[8],
    io_in_3v3[9],
    io_oeb[0],
    io_oeb[10],
    io_oeb[11],
    io_oeb[12],
    io_oeb[13],
    io_oeb[14],
    io_oeb[15],
    io_oeb[16],
    io_oeb[17],
    io_oeb[18],
    io_oeb[19],
    io_oeb[1],
    io_oeb[20],
    io_oeb[21],
    io_oeb[22],
    io_oeb[23],
    io_oeb[24],
    io_oeb[25],
    io_oeb[26],
    io_oeb[2],
    io_oeb[3],
    io_oeb[4],
    io_oeb[5],
    io_oeb[6],
    io_oeb[7],
    io_oeb[8],
    io_oeb[9],
    io_out[0],
    io_out[10],
    io_out[11],
    io_out[12],
    io_out[13],
    io_out[14],
    io_out[15],
    io_out[16],
    io_out[17],
    io_out[18],
    io_out[19],
    io_out[1],
    io_out[20],
    io_out[21],
    io_out[22],
    io_out[23],
    io_out[24],
    io_out[25],
    io_out[26],
    io_out[2],
    io_out[3],
    io_out[4],
    io_out[5],
    io_out[6],
    io_out[7],
    io_out[8],
    io_out[9],
    la_data_in[0],
    la_data_in[100],
    la_data_in[101],
    la_data_in[102],
    la_data_in[103],
    la_data_in[104],
    la_data_in[105],
    la_data_in[106],
    la_data_in[107],
    la_data_in[108],
    la_data_in[109],
    la_data_in[10],
    la_data_in[110],
    la_data_in[111],
    la_data_in[112],
    la_data_in[113],
    la_data_in[114],
    la_data_in[115],
    la_data_in[116],
    la_data_in[117],
    la_data_in[118],
    la_data_in[119],
    la_data_in[11],
    la_data_in[120],
    la_data_in[121],
    la_data_in[122],
    la_data_in[123],
    la_data_in[124],
    la_data_in[125],
    la_data_in[126],
    la_data_in[127],
    la_data_in[12],
    la_data_in[13],
    la_data_in[14],
    la_data_in[15],
    la_data_in[16],
    la_data_in[17],
    la_data_in[18],
    la_data_in[19],
    la_data_in[1],
    la_data_in[20],
    la_data_in[21],
    la_data_in[22],
    la_data_in[23],
    la_data_in[24],
    la_data_in[25],
    la_data_in[26],
    la_data_in[27],
    la_data_in[28],
    la_data_in[29],
    la_data_in[2],
    la_data_in[30],
    la_data_in[31],
    la_data_in[32],
    la_data_in[33],
    la_data_in[34],
    la_data_in[35],
    la_data_in[36],
    la_data_in[37],
    la_data_in[38],
    la_data_in[39],
    la_data_in[3],
    la_data_in[40],
    la_data_in[41],
    la_data_in[42],
    la_data_in[43],
    la_data_in[44],
    la_data_in[45],
    la_data_in[46],
    la_data_in[47],
    la_data_in[48],
    la_data_in[49],
    la_data_in[4],
    la_data_in[50],
    la_data_in[51],
    la_data_in[52],
    la_data_in[53],
    la_data_in[54],
    la_data_in[55],
    la_data_in[56],
    la_data_in[57],
    la_data_in[58],
    la_data_in[59],
    la_data_in[5],
    la_data_in[60],
    la_data_in[61],
    la_data_in[62],
    la_data_in[63],
    la_data_in[64],
    la_data_in[65],
    la_data_in[66],
    la_data_in[67],
    la_data_in[68],
    la_data_in[69],
    la_data_in[6],
    la_data_in[70],
    la_data_in[71],
    la_data_in[72],
    la_data_in[73],
    la_data_in[74],
    la_data_in[75],
    la_data_in[76],
    la_data_in[77],
    la_data_in[78],
    la_data_in[79],
    la_data_in[7],
    la_data_in[80],
    la_data_in[81],
    la_data_in[82],
    la_data_in[83],
    la_data_in[84],
    la_data_in[85],
    la_data_in[86],
    la_data_in[87],
    la_data_in[88],
    la_data_in[89],
    la_data_in[8],
    la_data_in[90],
    la_data_in[91],
    la_data_in[92],
    la_data_in[93],
    la_data_in[94],
    la_data_in[95],
    la_data_in[96],
    la_data_in[97],
    la_data_in[98],
    la_data_in[99],
    la_data_in[9],
    la_data_out[0],
    la_data_out[100],
    la_data_out[101],
    la_data_out[102],
    la_data_out[103],
    la_data_out[104],
    la_data_out[105],
    la_data_out[106],
    la_data_out[107],
    la_data_out[108],
    la_data_out[109],
    la_data_out[10],
    la_data_out[110],
    la_data_out[111],
    la_data_out[112],
    la_data_out[113],
    la_data_out[114],
    la_data_out[115],
    la_data_out[116],
    la_data_out[117],
    la_data_out[118],
    la_data_out[119],
    la_data_out[11],
    la_data_out[120],
    la_data_out[121],
    la_data_out[122],
    la_data_out[123],
    la_data_out[124],
    la_data_out[125],
    la_data_out[126],
    la_data_out[127],
    la_data_out[12],
    la_data_out[13],
    la_data_out[14],
    la_data_out[15],
    la_data_out[16],
    la_data_out[17],
    la_data_out[18],
    la_data_out[19],
    la_data_out[1],
    la_data_out[20],
    la_data_out[21],
    la_data_out[22],
    la_data_out[23],
    la_data_out[24],
    la_data_out[25],
    la_data_out[26],
    la_data_out[27],
    la_data_out[28],
    la_data_out[29],
    la_data_out[2],
    la_data_out[30],
    la_data_out[31],
    la_data_out[32],
    la_data_out[33],
    la_data_out[34],
    la_data_out[35],
    la_data_out[36],
    la_data_out[37],
    la_data_out[38],
    la_data_out[39],
    la_data_out[3],
    la_data_out[40],
    la_data_out[41],
    la_data_out[42],
    la_data_out[43],
    la_data_out[44],
    la_data_out[45],
    la_data_out[46],
    la_data_out[47],
    la_data_out[48],
    la_data_out[49],
    la_data_out[4],
    la_data_out[50],
    la_data_out[51],
    la_data_out[52],
    la_data_out[53],
    la_data_out[54],
    la_data_out[55],
    la_data_out[56],
    la_data_out[57],
    la_data_out[58],
    la_data_out[59],
    la_data_out[5],
    la_data_out[60],
    la_data_out[61],
    la_data_out[62],
    la_data_out[63],
    la_data_out[64],
    la_data_out[65],
    la_data_out[66],
    la_data_out[67],
    la_data_out[68],
    la_data_out[69],
    la_data_out[6],
    la_data_out[70],
    la_data_out[71],
    la_data_out[72],
    la_data_out[73],
    la_data_out[74],
    la_data_out[75],
    la_data_out[76],
    la_data_out[77],
    la_data_out[78],
    la_data_out[79],
    la_data_out[7],
    la_data_out[80],
    la_data_out[81],
    la_data_out[82],
    la_data_out[83],
    la_data_out[84],
    la_data_out[85],
    la_data_out[86],
    la_data_out[87],
    la_data_out[88],
    la_data_out[89],
    la_data_out[8],
    la_data_out[90],
    la_data_out[91],
    la_data_out[92],
    la_data_out[93],
    la_data_out[94],
    la_data_out[95],
    la_data_out[96],
    la_data_out[97],
    la_data_out[98],
    la_data_out[99],
    la_data_out[9],
    la_oenb[0],
    la_oenb[100],
    la_oenb[101],
    la_oenb[102],
    la_oenb[103],
    la_oenb[104],
    la_oenb[105],
    la_oenb[106],
    la_oenb[107],
    la_oenb[108],
    la_oenb[109],
    la_oenb[10],
    la_oenb[110],
    la_oenb[111],
    la_oenb[112],
    la_oenb[113],
    la_oenb[114],
    la_oenb[115],
    la_oenb[116],
    la_oenb[117],
    la_oenb[118],
    la_oenb[119],
    la_oenb[11],
    la_oenb[120],
    la_oenb[121],
    la_oenb[122],
    la_oenb[123],
    la_oenb[124],
    la_oenb[125],
    la_oenb[126],
    la_oenb[127],
    la_oenb[12],
    la_oenb[13],
    la_oenb[14],
    la_oenb[15],
    la_oenb[16],
    la_oenb[17],
    la_oenb[18],
    la_oenb[19],
    la_oenb[1],
    la_oenb[20],
    la_oenb[21],
    la_oenb[22],
    la_oenb[23],
    la_oenb[24],
    la_oenb[25],
    la_oenb[26],
    la_oenb[27],
    la_oenb[28],
    la_oenb[29],
    la_oenb[2],
    la_oenb[30],
    la_oenb[31],
    la_oenb[32],
    la_oenb[33],
    la_oenb[34],
    la_oenb[35],
    la_oenb[36],
    la_oenb[37],
    la_oenb[38],
    la_oenb[39],
    la_oenb[3],
    la_oenb[40],
    la_oenb[41],
    la_oenb[42],
    la_oenb[43],
    la_oenb[44],
    la_oenb[45],
    la_oenb[46],
    la_oenb[47],
    la_oenb[48],
    la_oenb[49],
    la_oenb[4],
    la_oenb[50],
    la_oenb[51],
    la_oenb[52],
    la_oenb[53],
    la_oenb[54],
    la_oenb[55],
    la_oenb[56],
    la_oenb[57],
    la_oenb[58],
    la_oenb[59],
    la_oenb[5],
    la_oenb[60],
    la_oenb[61],
    la_oenb[62],
    la_oenb[63],
    la_oenb[64],
    la_oenb[65],
    la_oenb[66],
    la_oenb[67],
    la_oenb[68],
    la_oenb[69],
    la_oenb[6],
    la_oenb[70],
    la_oenb[71],
    la_oenb[72],
    la_oenb[73],
    la_oenb[74],
    la_oenb[75],
    la_oenb[76],
    la_oenb[77],
    la_oenb[78],
    la_oenb[79],
    la_oenb[7],
    la_oenb[80],
    la_oenb[81],
    la_oenb[82],
    la_oenb[83],
    la_oenb[84],
    la_oenb[85],
    la_oenb[86],
    la_oenb[87],
    la_oenb[88],
    la_oenb[89],
    la_oenb[8],
    la_oenb[90],
    la_oenb[91],
    la_oenb[92],
    la_oenb[93],
    la_oenb[94],
    la_oenb[95],
    la_oenb[96],
    la_oenb[97],
    la_oenb[98],
    la_oenb[99],
    la_oenb[9],
    user_clock2,
    user_irq[0],
    user_irq[1],
    user_irq[2],
    vccd1,
    vccd2,
    vdda1,
    vdda2,
    vssa1,
    vssa2,
    vssd1,
    vssd2,
    wb_clk_i,
    wb_rst_i,
    wbs_ack_o,
    wbs_adr_i[0],
    wbs_adr_i[10],
    wbs_adr_i[11],
    wbs_adr_i[12],
    wbs_adr_i[13],
    wbs_adr_i[14],
    wbs_adr_i[15],
    wbs_adr_i[16],
    wbs_adr_i[17],
    wbs_adr_i[18],
    wbs_adr_i[19],
    wbs_adr_i[1],
    wbs_adr_i[20],
    wbs_adr_i[21],
    wbs_adr_i[22],
    wbs_adr_i[23],
    wbs_adr_i[24],
    wbs_adr_i[25],
    wbs_adr_i[26],
    wbs_adr_i[27],
    wbs_adr_i[28],
    wbs_adr_i[29],
    wbs_adr_i[2],
    wbs_adr_i[30],
    wbs_adr_i[31],
    wbs_adr_i[3],
    wbs_adr_i[4],
    wbs_adr_i[5],
    wbs_adr_i[6],
    wbs_adr_i[7],
    wbs_adr_i[8],
    wbs_adr_i[9],
    wbs_cyc_i,
    wbs_dat_i[0],
    wbs_dat_i[10],
    wbs_dat_i[11],
    wbs_dat_i[12],
    wbs_dat_i[13],
    wbs_dat_i[14],
    wbs_dat_i[15],
    wbs_dat_i[16],
    wbs_dat_i[17],
    wbs_dat_i[18],
    wbs_dat_i[19],
    wbs_dat_i[1],
    wbs_dat_i[20],
    wbs_dat_i[21],
    wbs_dat_i[22],
    wbs_dat_i[23],
    wbs_dat_i[24],
    wbs_dat_i[25],
    wbs_dat_i[26],
    wbs_dat_i[27],
    wbs_dat_i[28],
    wbs_dat_i[29],
    wbs_dat_i[2],
    wbs_dat_i[30],
    wbs_dat_i[31],
    wbs_dat_i[3],
    wbs_dat_i[4],
    wbs_dat_i[5],
    wbs_dat_i[6],
    wbs_dat_i[7],
    wbs_dat_i[8],
    wbs_dat_i[9],
    wbs_dat_o[0],
    wbs_dat_o[10],
    wbs_dat_o[11],
    wbs_dat_o[12],
    wbs_dat_o[13],
    wbs_dat_o[14],
    wbs_dat_o[15],
    wbs_dat_o[16],
    wbs_dat_o[17],
    wbs_dat_o[18],
    wbs_dat_o[19],
    wbs_dat_o[1],
    wbs_dat_o[20],
    wbs_dat_o[21],
    wbs_dat_o[22],
    wbs_dat_o[23],
    wbs_dat_o[24],
    wbs_dat_o[25],
    wbs_dat_o[26],
    wbs_dat_o[27],
    wbs_dat_o[28],
    wbs_dat_o[29],
    wbs_dat_o[2],
    wbs_dat_o[30],
    wbs_dat_o[31],
    wbs_dat_o[3],
    wbs_dat_o[4],
    wbs_dat_o[5],
    wbs_dat_o[6],
    wbs_dat_o[7],
    wbs_dat_o[8],
    wbs_dat_o[9],
    wbs_sel_i[0],
    wbs_sel_i[1],
    wbs_sel_i[2],
    wbs_sel_i[3],
    wbs_stb_i,
    wbs_we_i
);
        inout gpio_analog[0];
        inout gpio_analog[10];
        inout gpio_analog[11];
        inout gpio_analog[12];
        inout gpio_analog[13];
        inout gpio_analog[14];
        inout gpio_analog[15];
        inout gpio_analog[16];
        inout gpio_analog[17];
        inout gpio_analog[1];
        inout gpio_analog[2];
        inout gpio_analog[3];
        inout gpio_analog[4];
        inout gpio_analog[5];
        inout gpio_analog[6];
        inout gpio_analog[7];
        inout gpio_analog[8];
        inout gpio_analog[9];
        inout gpio_noesd[0];
        inout gpio_noesd[10];
        inout gpio_noesd[11];
        inout gpio_noesd[12];
        inout gpio_noesd[13];
        inout gpio_noesd[14];
        inout gpio_noesd[15];
        inout gpio_noesd[16];
        inout gpio_noesd[17];
        inout gpio_noesd[1];
        inout gpio_noesd[2];
        inout gpio_noesd[3];
        inout gpio_noesd[4];
        inout gpio_noesd[5];
        inout gpio_noesd[6];
        inout gpio_noesd[7];
        inout gpio_noesd[8];
        inout gpio_noesd[9];
        inout io_analog[0];
        inout io_analog[10];
        inout io_analog[1];
        inout io_analog[2];
        inout io_analog[3];
        inout io_analog[4];
        inout io_analog[5];
        inout io_analog[6];
        inout io_analog[7];
        inout io_analog[8];
        inout io_analog[9];
        inout io_clamp_high[0];
        inout io_clamp_high[1];
        inout io_clamp_high[2];
        inout io_clamp_low[0];
        inout io_clamp_low[1];
        inout io_clamp_low[2];
        inout io_in[0];
        inout io_in[10];
        inout io_in[11];
        inout io_in[12];
        inout io_in[13];
        inout io_in[14];
        inout io_in[15];
        inout io_in[16];
        inout io_in[17];
        inout io_in[18];
        inout io_in[19];
        inout io_in[1];
        inout io_in[20];
        inout io_in[21];
        inout io_in[22];
        inout io_in[23];
        inout io_in[24];
        inout io_in[25];
        inout io_in[26];
        inout io_in[2];
        inout io_in[3];
        inout io_in[4];
        inout io_in[5];
        inout io_in[6];
        inout io_in[7];
        inout io_in[8];
        inout io_in[9];
        inout io_in_3v3[0];
        inout io_in_3v3[10];
        inout io_in_3v3[11];
        inout io_in_3v3[12];
        inout io_in_3v3[13];
        inout io_in_3v3[14];
        inout io_in_3v3[15];
        inout io_in_3v3[16];
        inout io_in_3v3[17];
        inout io_in_3v3[18];
        inout io_in_3v3[19];
        inout io_in_3v3[1];
        inout io_in_3v3[20];
        inout io_in_3v3[21];
        inout io_in_3v3[22];
        inout io_in_3v3[23];
        inout io_in_3v3[24];
        inout io_in_3v3[25];
        inout io_in_3v3[26];
        inout io_in_3v3[2];
        inout io_in_3v3[3];
        inout io_in_3v3[4];
        inout io_in_3v3[5];
        inout io_in_3v3[6];
        inout io_in_3v3[7];
        inout io_in_3v3[8];
        inout io_in_3v3[9];
        inout io_oeb[0];
        inout io_oeb[10];
        inout io_oeb[11];
        inout io_oeb[12];
        inout io_oeb[13];
        inout io_oeb[14];
        inout io_oeb[15];
        inout io_oeb[16];
        inout io_oeb[17];
        inout io_oeb[18];
        inout io_oeb[19];
        inout io_oeb[1];
        inout io_oeb[20];
        inout io_oeb[21];
        inout io_oeb[22];
        inout io_oeb[23];
        inout io_oeb[24];
        inout io_oeb[25];
        inout io_oeb[26];
        inout io_oeb[2];
        inout io_oeb[3];
        inout io_oeb[4];
        inout io_oeb[5];
        inout io_oeb[6];
        inout io_oeb[7];
        inout io_oeb[8];
        inout io_oeb[9];
        inout io_out[0];
        inout io_out[10];
        inout io_out[11];
        inout io_out[12];
        inout io_out[13];
        inout io_out[14];
        inout io_out[15];
        inout io_out[16];
        inout io_out[17];
        inout io_out[18];
        inout io_out[19];
        inout io_out[1];
        inout io_out[20];
        inout io_out[21];
        inout io_out[22];
        inout io_out[23];
        inout io_out[24];
        inout io_out[25];
        inout io_out[26];
        inout io_out[2];
        inout io_out[3];
        inout io_out[4];
        inout io_out[5];
        inout io_out[6];
        inout io_out[7];
        inout io_out[8];
        inout io_out[9];
        inout la_data_in[0];
        inout la_data_in[100];
        inout la_data_in[101];
        inout la_data_in[102];
        inout la_data_in[103];
        inout la_data_in[104];
        inout la_data_in[105];
        inout la_data_in[106];
        inout la_data_in[107];
        inout la_data_in[108];
        inout la_data_in[109];
        inout la_data_in[10];
        inout la_data_in[110];
        inout la_data_in[111];
        inout la_data_in[112];
        inout la_data_in[113];
        inout la_data_in[114];
        inout la_data_in[115];
        inout la_data_in[116];
        inout la_data_in[117];
        inout la_data_in[118];
        inout la_data_in[119];
        inout la_data_in[11];
        inout la_data_in[120];
        inout la_data_in[121];
        inout la_data_in[122];
        inout la_data_in[123];
        inout la_data_in[124];
        inout la_data_in[125];
        inout la_data_in[126];
        inout la_data_in[127];
        inout la_data_in[12];
        inout la_data_in[13];
        inout la_data_in[14];
        inout la_data_in[15];
        inout la_data_in[16];
        inout la_data_in[17];
        inout la_data_in[18];
        inout la_data_in[19];
        inout la_data_in[1];
        inout la_data_in[20];
        inout la_data_in[21];
        inout la_data_in[22];
        inout la_data_in[23];
        inout la_data_in[24];
        inout la_data_in[25];
        inout la_data_in[26];
        inout la_data_in[27];
        inout la_data_in[28];
        inout la_data_in[29];
        inout la_data_in[2];
        inout la_data_in[30];
        inout la_data_in[31];
        inout la_data_in[32];
        inout la_data_in[33];
        inout la_data_in[34];
        inout la_data_in[35];
        inout la_data_in[36];
        inout la_data_in[37];
        inout la_data_in[38];
        inout la_data_in[39];
        inout la_data_in[3];
        inout la_data_in[40];
        inout la_data_in[41];
        inout la_data_in[42];
        inout la_data_in[43];
        inout la_data_in[44];
        inout la_data_in[45];
        inout la_data_in[46];
        inout la_data_in[47];
        inout la_data_in[48];
        inout la_data_in[49];
        inout la_data_in[4];
        inout la_data_in[50];
        inout la_data_in[51];
        inout la_data_in[52];
        inout la_data_in[53];
        inout la_data_in[54];
        inout la_data_in[55];
        inout la_data_in[56];
        inout la_data_in[57];
        inout la_data_in[58];
        inout la_data_in[59];
        inout la_data_in[5];
        inout la_data_in[60];
        inout la_data_in[61];
        inout la_data_in[62];
        inout la_data_in[63];
        inout la_data_in[64];
        inout la_data_in[65];
        inout la_data_in[66];
        inout la_data_in[67];
        inout la_data_in[68];
        inout la_data_in[69];
        inout la_data_in[6];
        inout la_data_in[70];
        inout la_data_in[71];
        inout la_data_in[72];
        inout la_data_in[73];
        inout la_data_in[74];
        inout la_data_in[75];
        inout la_data_in[76];
        inout la_data_in[77];
        inout la_data_in[78];
        inout la_data_in[79];
        inout la_data_in[7];
        inout la_data_in[80];
        inout la_data_in[81];
        inout la_data_in[82];
        inout la_data_in[83];
        inout la_data_in[84];
        inout la_data_in[85];
        inout la_data_in[86];
        inout la_data_in[87];
        inout la_data_in[88];
        inout la_data_in[89];
        inout la_data_in[8];
        inout la_data_in[90];
        inout la_data_in[91];
        inout la_data_in[92];
        inout la_data_in[93];
        inout la_data_in[94];
        inout la_data_in[95];
        inout la_data_in[96];
        inout la_data_in[97];
        inout la_data_in[98];
        inout la_data_in[99];
        inout la_data_in[9];
        inout la_data_out[0];
        inout la_data_out[100];
        inout la_data_out[101];
        inout la_data_out[102];
        inout la_data_out[103];
        inout la_data_out[104];
        inout la_data_out[105];
        inout la_data_out[106];
        inout la_data_out[107];
        inout la_data_out[108];
        inout la_data_out[109];
        inout la_data_out[10];
        inout la_data_out[110];
        inout la_data_out[111];
        inout la_data_out[112];
        inout la_data_out[113];
        inout la_data_out[114];
        inout la_data_out[115];
        inout la_data_out[116];
        inout la_data_out[117];
        inout la_data_out[118];
        inout la_data_out[119];
        inout la_data_out[11];
        inout la_data_out[120];
        inout la_data_out[121];
        inout la_data_out[122];
        inout la_data_out[123];
        inout la_data_out[124];
        inout la_data_out[125];
        inout la_data_out[126];
        inout la_data_out[127];
        inout la_data_out[12];
        inout la_data_out[13];
        inout la_data_out[14];
        inout la_data_out[15];
        inout la_data_out[16];
        inout la_data_out[17];
        inout la_data_out[18];
        inout la_data_out[19];
        inout la_data_out[1];
        inout la_data_out[20];
        inout la_data_out[21];
        inout la_data_out[22];
        inout la_data_out[23];
        inout la_data_out[24];
        inout la_data_out[25];
        inout la_data_out[26];
        inout la_data_out[27];
        inout la_data_out[28];
        inout la_data_out[29];
        inout la_data_out[2];
        inout la_data_out[30];
        inout la_data_out[31];
        inout la_data_out[32];
        inout la_data_out[33];
        inout la_data_out[34];
        inout la_data_out[35];
        inout la_data_out[36];
        inout la_data_out[37];
        inout la_data_out[38];
        inout la_data_out[39];
        inout la_data_out[3];
        inout la_data_out[40];
        inout la_data_out[41];
        inout la_data_out[42];
        inout la_data_out[43];
        inout la_data_out[44];
        inout la_data_out[45];
        inout la_data_out[46];
        inout la_data_out[47];
        inout la_data_out[48];
        inout la_data_out[49];
        inout la_data_out[4];
        inout la_data_out[50];
        inout la_data_out[51];
        inout la_data_out[52];
        inout la_data_out[53];
        inout la_data_out[54];
        inout la_data_out[55];
        inout la_data_out[56];
        inout la_data_out[57];
        inout la_data_out[58];
        inout la_data_out[59];
        inout la_data_out[5];
        inout la_data_out[60];
        inout la_data_out[61];
        inout la_data_out[62];
        inout la_data_out[63];
        inout la_data_out[64];
        inout la_data_out[65];
        inout la_data_out[66];
        inout la_data_out[67];
        inout la_data_out[68];
        inout la_data_out[69];
        inout la_data_out[6];
        inout la_data_out[70];
        inout la_data_out[71];
        inout la_data_out[72];
        inout la_data_out[73];
        inout la_data_out[74];
        inout la_data_out[75];
        inout la_data_out[76];
        inout la_data_out[77];
        inout la_data_out[78];
        inout la_data_out[79];
        inout la_data_out[7];
        inout la_data_out[80];
        inout la_data_out[81];
        inout la_data_out[82];
        inout la_data_out[83];
        inout la_data_out[84];
        inout la_data_out[85];
        inout la_data_out[86];
        inout la_data_out[87];
        inout la_data_out[88];
        inout la_data_out[89];
        inout la_data_out[8];
        inout la_data_out[90];
        inout la_data_out[91];
        inout la_data_out[92];
        inout la_data_out[93];
        inout la_data_out[94];
        inout la_data_out[95];
        inout la_data_out[96];
        inout la_data_out[97];
        inout la_data_out[98];
        inout la_data_out[99];
        inout la_data_out[9];
        inout la_oenb[0];
        inout la_oenb[100];
        inout la_oenb[101];
        inout la_oenb[102];
        inout la_oenb[103];
        inout la_oenb[104];
        inout la_oenb[105];
        inout la_oenb[106];
        inout la_oenb[107];
        inout la_oenb[108];
        inout la_oenb[109];
        inout la_oenb[10];
        inout la_oenb[110];
        inout la_oenb[111];
        inout la_oenb[112];
        inout la_oenb[113];
        inout la_oenb[114];
        inout la_oenb[115];
        inout la_oenb[116];
        inout la_oenb[117];
        inout la_oenb[118];
        inout la_oenb[119];
        inout la_oenb[11];
        inout la_oenb[120];
        inout la_oenb[121];
        inout la_oenb[122];
        inout la_oenb[123];
        inout la_oenb[124];
        inout la_oenb[125];
        inout la_oenb[126];
        inout la_oenb[127];
        inout la_oenb[12];
        inout la_oenb[13];
        inout la_oenb[14];
        inout la_oenb[15];
        inout la_oenb[16];
        inout la_oenb[17];
        inout la_oenb[18];
        inout la_oenb[19];
        inout la_oenb[1];
        inout la_oenb[20];
        inout la_oenb[21];
        inout la_oenb[22];
        inout la_oenb[23];
        inout la_oenb[24];
        inout la_oenb[25];
        inout la_oenb[26];
        inout la_oenb[27];
        inout la_oenb[28];
        inout la_oenb[29];
        inout la_oenb[2];
        inout la_oenb[30];
        inout la_oenb[31];
        inout la_oenb[32];
        inout la_oenb[33];
        inout la_oenb[34];
        inout la_oenb[35];
        inout la_oenb[36];
        inout la_oenb[37];
        inout la_oenb[38];
        inout la_oenb[39];
        inout la_oenb[3];
        inout la_oenb[40];
        inout la_oenb[41];
        inout la_oenb[42];
        inout la_oenb[43];
        inout la_oenb[44];
        inout la_oenb[45];
        inout la_oenb[46];
        inout la_oenb[47];
        inout la_oenb[48];
        inout la_oenb[49];
        inout la_oenb[4];
        inout la_oenb[50];
        inout la_oenb[51];
        inout la_oenb[52];
        inout la_oenb[53];
        inout la_oenb[54];
        inout la_oenb[55];
        inout la_oenb[56];
        inout la_oenb[57];
        inout la_oenb[58];
        inout la_oenb[59];
        inout la_oenb[5];
        inout la_oenb[60];
        inout la_oenb[61];
        inout la_oenb[62];
        inout la_oenb[63];
        inout la_oenb[64];
        inout la_oenb[65];
        inout la_oenb[66];
        inout la_oenb[67];
        inout la_oenb[68];
        inout la_oenb[69];
        inout la_oenb[6];
        inout la_oenb[70];
        inout la_oenb[71];
        inout la_oenb[72];
        inout la_oenb[73];
        inout la_oenb[74];
        inout la_oenb[75];
        inout la_oenb[76];
        inout la_oenb[77];
        inout la_oenb[78];
        inout la_oenb[79];
        inout la_oenb[7];
        inout la_oenb[80];
        inout la_oenb[81];
        inout la_oenb[82];
        inout la_oenb[83];
        inout la_oenb[84];
        inout la_oenb[85];
        inout la_oenb[86];
        inout la_oenb[87];
        inout la_oenb[88];
        inout la_oenb[89];
        inout la_oenb[8];
        inout la_oenb[90];
        inout la_oenb[91];
        inout la_oenb[92];
        inout la_oenb[93];
        inout la_oenb[94];
        inout la_oenb[95];
        inout la_oenb[96];
        inout la_oenb[97];
        inout la_oenb[98];
        inout la_oenb[99];
        inout la_oenb[9];
        inout user_clock2;
        inout user_irq[0];
        inout user_irq[1];
        inout user_irq[2];
        inout vccd1;
        inout vccd2;
        inout vdda1;
        inout vdda2;
        inout vssa1;
        inout vssa2;
        inout vssd1;
        inout vssd2;
        inout wb_clk_i;
        inout wb_rst_i;
        inout wbs_ack_o;
        inout wbs_adr_i[0];
        inout wbs_adr_i[10];
        inout wbs_adr_i[11];
        inout wbs_adr_i[12];
        inout wbs_adr_i[13];
        inout wbs_adr_i[14];
        inout wbs_adr_i[15];
        inout wbs_adr_i[16];
        inout wbs_adr_i[17];
        inout wbs_adr_i[18];
        inout wbs_adr_i[19];
        inout wbs_adr_i[1];
        inout wbs_adr_i[20];
        inout wbs_adr_i[21];
        inout wbs_adr_i[22];
        inout wbs_adr_i[23];
        inout wbs_adr_i[24];
        inout wbs_adr_i[25];
        inout wbs_adr_i[26];
        inout wbs_adr_i[27];
        inout wbs_adr_i[28];
        inout wbs_adr_i[29];
        inout wbs_adr_i[2];
        inout wbs_adr_i[30];
        inout wbs_adr_i[31];
        inout wbs_adr_i[3];
        inout wbs_adr_i[4];
        inout wbs_adr_i[5];
        inout wbs_adr_i[6];
        inout wbs_adr_i[7];
        inout wbs_adr_i[8];
        inout wbs_adr_i[9];
        inout wbs_cyc_i;
        inout wbs_dat_i[0];
        inout wbs_dat_i[10];
        inout wbs_dat_i[11];
        inout wbs_dat_i[12];
        inout wbs_dat_i[13];
        inout wbs_dat_i[14];
        inout wbs_dat_i[15];
        inout wbs_dat_i[16];
        inout wbs_dat_i[17];
        inout wbs_dat_i[18];
        inout wbs_dat_i[19];
        inout wbs_dat_i[1];
        inout wbs_dat_i[20];
        inout wbs_dat_i[21];
        inout wbs_dat_i[22];
        inout wbs_dat_i[23];
        inout wbs_dat_i[24];
        inout wbs_dat_i[25];
        inout wbs_dat_i[26];
        inout wbs_dat_i[27];
        inout wbs_dat_i[28];
        inout wbs_dat_i[29];
        inout wbs_dat_i[2];
        inout wbs_dat_i[30];
        inout wbs_dat_i[31];
        inout wbs_dat_i[3];
        inout wbs_dat_i[4];
        inout wbs_dat_i[5];
        inout wbs_dat_i[6];
        inout wbs_dat_i[7];
        inout wbs_dat_i[8];
        inout wbs_dat_i[9];
        inout wbs_dat_o[0];
        inout wbs_dat_o[10];
        inout wbs_dat_o[11];
        inout wbs_dat_o[12];
        inout wbs_dat_o[13];
        inout wbs_dat_o[14];
        inout wbs_dat_o[15];
        inout wbs_dat_o[16];
        inout wbs_dat_o[17];
        inout wbs_dat_o[18];
        inout wbs_dat_o[19];
        inout wbs_dat_o[1];
        inout wbs_dat_o[20];
        inout wbs_dat_o[21];
        inout wbs_dat_o[22];
        inout wbs_dat_o[23];
        inout wbs_dat_o[24];
        inout wbs_dat_o[25];
        inout wbs_dat_o[26];
        inout wbs_dat_o[27];
        inout wbs_dat_o[28];
        inout wbs_dat_o[29];
        inout wbs_dat_o[2];
        inout wbs_dat_o[30];
        inout wbs_dat_o[31];
        inout wbs_dat_o[3];
        inout wbs_dat_o[4];
        inout wbs_dat_o[5];
        inout wbs_dat_o[6];
        inout wbs_dat_o[7];
        inout wbs_dat_o[8];
        inout wbs_dat_o[9];
        inout wbs_sel_i[0];
        inout wbs_sel_i[1];
        inout wbs_sel_i[2];
        inout wbs_sel_i[3];
        inout wbs_stb_i;
        inout wbs_we_i;
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // USER_ANALOG_PROJECT_WRAPPER


//--------EOF---------

`ifndef SKY130_HILAS_DAC6BIT01
`define SKY130_HILAS_DAC6BIT01

/**
 * sky130_hilas_DAC6bit01: None
 *
 * Verilog wrapper for sky130_hilas_DAC6bit01.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_DAC6bit01 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_DAC6bit01 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_DAC6BIT01


//--------EOF---------

`ifndef SKY130_HILAS_SWC2X2VARACTOR
`define SKY130_HILAS_SWC2X2VARACTOR

/**
 * sky130_hilas_swc2x2varactor: ??  Is this part of the library?
 *
 * Verilog wrapper for sky130_hilas_swc2x2varactor.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_swc2x2varactor (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_swc2x2varactor (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_SWC2X2VARACTOR


//--------EOF---------

`ifndef SKY130_HILAS_LI2M2
`define SKY130_HILAS_LI2M2

/**
 * sky130_hilas_li2m2: local interconnect to m2 contact
 *
 * Verilog wrapper for sky130_hilas_li2m2.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_li2m2 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_li2m2 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_LI2M2


//--------EOF---------

`ifndef SKY130_HILAS_TOPLEVELTEXTSTRUCTURE
`define SKY130_HILAS_TOPLEVELTEXTSTRUCTURE

/**
 * sky130_hilas_TopLevelTextStructure: top level test structure
 *
 * Verilog wrapper for sky130_hilas_TopLevelTextStructure.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_TopLevelTextStructure (
    DIG23,
    DIG22,
    DIG21,
    DIG29,
    DIG28,
    DIG27,
    DIG26,
    DIG25,
    DIG20,
    DIG19,
    DIG18,
    DIG17,
    DIG16,
    DIG15,
    DIG14,
    DIG13,
    DIG12,
    DIG11,
    DIG10,
    DIG09,
    DIG08,
    DIG07,
    DIG06,
    DIG05,
    DIG04,
    DIG03,
    DIG02,
    DIG01,
    GENERALGATE02,
    DRAINOUT,
    ROWTERM2,
    COLUMN2,
    COLUMN1,
    GATE2,
    DRAININJECT,
    VTUN,
    VREFCHAR,
    CHAROUTPUT,
    LARGECAPACITOR,
    DRAIN6N,
    DRAIN6P,
    DRAIN5P,
    DARIN4P,
    DRAIN5N,
    DRAIN4N,
    DRAIN3P,
    DRAIN2P,
    DRAIN3N,
    SOURCEN,
    SOURCEP,
    GATE1,
    VINJ,
    VGND,
    VPWR,
    VNB,
    VPB
);
        inout DIG23;
        inout DIG22;
        inout DIG21;
        inout DIG29;
        inout DIG28;
        inout DIG27;
        inout DIG26;
        inout DIG25;
        inout DIG20;
        inout DIG19;
        inout DIG18;
        inout DIG17;
        inout DIG16;
        inout DIG15;
        inout DIG14;
        inout DIG13;
        inout DIG12;
        inout DIG11;
        inout DIG10;
        inout DIG09;
        inout DIG08;
        inout DIG07;
        inout DIG06;
        inout DIG05;
        inout DIG04;
        inout DIG03;
        inout DIG02;
        inout DIG01;
        inout GENERALGATE02;
        inout DRAINOUT;
        inout ROWTERM2;
        inout COLUMN2;
        inout COLUMN1;
        inout GATE2;
        inout DRAININJECT;
        inout VTUN;
        inout VREFCHAR;
        inout CHAROUTPUT;
        inout LARGECAPACITOR;
        inout DRAIN6N;
        inout DRAIN6P;
        inout DRAIN5P;
        inout DARIN4P;
        inout DRAIN5N;
        inout DRAIN4N;
        inout DRAIN3P;
        inout DRAIN2P;
        inout DRAIN3N;
        inout SOURCEN;
        inout SOURCEP;
        inout GATE1;
        inout VINJ;
        inout VGND;
        inout VPWR;
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_TopLevelTextStructure (
    DIG23,
    DIG22,
    DIG21,
    DIG29,
    DIG28,
    DIG27,
    DIG26,
    DIG25,
    DIG20,
    DIG19,
    DIG18,
    DIG17,
    DIG16,
    DIG15,
    DIG14,
    DIG13,
    DIG12,
    DIG11,
    DIG10,
    DIG09,
    DIG08,
    DIG07,
    DIG06,
    DIG05,
    DIG04,
    DIG03,
    DIG02,
    DIG01,
    GENERALGATE02,
    DRAINOUT,
    ROWTERM2,
    COLUMN2,
    COLUMN1,
    GATE2,
    DRAININJECT,
    VTUN,
    VREFCHAR,
    CHAROUTPUT,
    LARGECAPACITOR,
    DRAIN6N,
    DRAIN6P,
    DRAIN5P,
    DARIN4P,
    DRAIN5N,
    DRAIN4N,
    DRAIN3P,
    DRAIN2P,
    DRAIN3N,
    SOURCEN,
    SOURCEP,
    GATE1,
    VINJ
);
        inout DIG23;
        inout DIG22;
        inout DIG21;
        inout DIG29;
        inout DIG28;
        inout DIG27;
        inout DIG26;
        inout DIG25;
        inout DIG20;
        inout DIG19;
        inout DIG18;
        inout DIG17;
        inout DIG16;
        inout DIG15;
        inout DIG14;
        inout DIG13;
        inout DIG12;
        inout DIG11;
        inout DIG10;
        inout DIG09;
        inout DIG08;
        inout DIG07;
        inout DIG06;
        inout DIG05;
        inout DIG04;
        inout DIG03;
        inout DIG02;
        inout DIG01;
        inout GENERALGATE02;
        inout DRAINOUT;
        inout ROWTERM2;
        inout COLUMN2;
        inout COLUMN1;
        inout GATE2;
        inout DRAININJECT;
        inout VTUN;
        inout VREFCHAR;
        inout CHAROUTPUT;
        inout LARGECAPACITOR;
        inout DRAIN6N;
        inout DRAIN6P;
        inout DRAIN5P;
        inout DARIN4P;
        inout DRAIN5N;
        inout DRAIN4N;
        inout DRAIN3P;
        inout DRAIN2P;
        inout DRAIN3N;
        inout SOURCEN;
        inout SOURCEP;
        inout GATE1;
        inout VINJ;
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_TOPLEVELTEXTSTRUCTURE


//--------EOF---------

`ifndef SKY130_HILAS_CAPACITORARRAY01
`define SKY130_HILAS_CAPACITORARRAY01

/**
 * sky130_hilas_capacitorArray01: selectable capacitor array
 *
 * Verilog wrapper for sky130_hilas_capacitorArray01.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_capacitorArray01 (
    CAPTERM2,
    CAPTERM1,
    VINJ,
    GATESELECT,
    VTUN,
    GATE,
    DRAIN2,
    DRAIN1,
    DRAIN4,
    DRAIN3,
    VGND,
    VNB,
    VPB
);
        inout CAPTERM2;
        inout CAPTERM1;
        inout VINJ;
        inout GATESELECT;
        inout VTUN;
        inout GATE;
        inout DRAIN2;
        inout DRAIN1;
        inout DRAIN4;
        inout DRAIN3;
        inout VGND;
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_capacitorArray01 (
    CAPTERM2,
    CAPTERM1,
    VINJ,
    GATESELECT,
    VTUN,
    GATE,
    DRAIN2,
    DRAIN1,
    DRAIN4,
    DRAIN3
);
        inout CAPTERM2;
        inout CAPTERM1;
        inout VINJ;
        inout GATESELECT;
        inout VTUN;
        inout GATE;
        inout DRAIN2;
        inout DRAIN1;
        inout DRAIN4;
        inout DRAIN3;
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_CAPACITORARRAY01


//--------EOF---------

`ifndef SKY130_HILAS_PFETDEVICE01A
`define SKY130_HILAS_PFETDEVICE01A

/**
 * sky130_hilas_pFETdevice01a: pFET transistor used in DAC block
 *
 * Verilog wrapper for sky130_hilas_pFETdevice01a.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_pFETdevice01a (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_pFETdevice01a (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_PFETDEVICE01A


//--------EOF---------

`ifndef SKY130_HILAS_TA2CELL_1FG
`define SKY130_HILAS_TA2CELL_1FG

/**
 * sky130_hilas_TA2Cell_1FG: Two transimpedance amps with one (of two) amplifiers using floating-gate
  inputs. FG amplifier with wide linear range.
 *
 * Verilog wrapper for sky130_hilas_TA2Cell_1FG.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_TA2Cell_1FG (
    VIN12,
    VIN11,
    VIN21,
    VIN22,
    VINJ,
    OUTPUT1,
    OUTPUT2,
    DRAIN1,
    DRAIN2,
    COLSEL2,
    GATE2,
    GATE1,
    COLSEL1,
    VTUN,
    VPWR,
    VGND,
    VNB,
    VPB
);
        inout VIN12;
        inout VIN11;
        inout VIN21;
        inout VIN22;
        inout VINJ;
        inout OUTPUT1;
        inout OUTPUT2;
        inout DRAIN1;
        inout DRAIN2;
        inout COLSEL2;
        inout GATE2;
        inout GATE1;
        inout COLSEL1;
        inout VTUN;
        inout VPWR;
        inout VGND;
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_TA2Cell_1FG (
    VIN12,
    VIN11,
    VIN21,
    VIN22,
    VINJ,
    OUTPUT1,
    OUTPUT2,
    DRAIN1,
    DRAIN2,
    COLSEL2,
    GATE2,
    GATE1,
    COLSEL1,
    VTUN
);
        inout VIN12;
        inout VIN11;
        inout VIN21;
        inout VIN22;
        inout VINJ;
        inout OUTPUT1;
        inout OUTPUT2;
        inout DRAIN1;
        inout DRAIN2;
        inout COLSEL2;
        inout GATE2;
        inout GATE1;
        inout COLSEL1;
        inout VTUN;
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_TA2CELL_1FG


//--------EOF---------

`ifndef SKY130_HILAS_TUNVARACTORCAPCITOR
`define SKY130_HILAS_TUNVARACTORCAPCITOR

/**
 * sky130_hilas_TunVaractorCapcitor: Tunneling capacitor using a standard varactor capacitor
 *
 * Verilog wrapper for sky130_hilas_TunVaractorCapcitor.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_TunVaractorCapcitor (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_TunVaractorCapcitor (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_TUNVARACTORCAPCITOR


//--------EOF---------

`ifndef SKY130_HILAS_FGVARACTORCAPACITOR
`define SKY130_HILAS_FGVARACTORCAPACITOR

/**
 * sky130_hilas_FGVaractorCapacitor: varactor cap for floating-gate charge storage
 *
 * Verilog wrapper for sky130_hilas_FGVaractorCapacitor.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_FGVaractorCapacitor (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_FGVaractorCapacitor (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_FGVARACTORCAPACITOR


//--------EOF---------

`ifndef SKY130_HILAS_TACOREBLOCK2
`define SKY130_HILAS_TACOREBLOCK2

/**
 * sky130_hilas_TACoreBlock2: None
 *
 * Verilog wrapper for sky130_hilas_TACoreBlock2.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_TACoreBlock2 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_TACoreBlock2 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_TACOREBLOCK2


//--------EOF---------

`ifndef SKY130_HILAS_LI2M1
`define SKY130_HILAS_LI2M1

/**
 * sky130_hilas_li2m1: local interconnect to m1 contact
 *
 * Verilog wrapper for sky130_hilas_li2m1.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_li2m1 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_li2m1 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_LI2M1


//--------EOF---------

`ifndef SKY130_HILAS_FGBIASWEAKGATE2X1CELL
`define SKY130_HILAS_FGBIASWEAKGATE2X1CELL

/**
 * sky130_hilas_FGBiasWeakGate2x1cell: 2x1 array of FG switch cells configured as pFET current sources with weak capacitive gate inputs
 *
 * Verilog wrapper for sky130_hilas_FGBiasWeakGate2x1cell.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_FGBiasWeakGate2x1cell (
    DRAIN1,
    VIN11,
    ROW1,
    ROW2,
    VINJ,
    COLSEL1,
    GATE1,
    VTUN,
    DRAIN2,
    VIN12,
    COMMONSOURCE,
    VGND,
    VNB,
    VPB
);
        inout DRAIN1;
        inout VIN11;
        inout ROW1;
        inout ROW2;
        inout VINJ;
        inout COLSEL1;
        inout GATE1;
        inout VTUN;
        inout DRAIN2;
        inout VIN12;
        inout COMMONSOURCE;
        inout VGND;
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_FGBiasWeakGate2x1cell (
    DRAIN1,
    VIN11,
    ROW1,
    ROW2,
    VINJ,
    COLSEL1,
    GATE1,
    VTUN,
    DRAIN2,
    VIN12,
    COMMONSOURCE
);
        inout DRAIN1;
        inout VIN11;
        inout ROW1;
        inout ROW2;
        inout VINJ;
        inout COLSEL1;
        inout GATE1;
        inout VTUN;
        inout DRAIN2;
        inout VIN12;
        inout COMMONSOURCE;
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_FGBIASWEAKGATE2X1CELL


//--------EOF---------

`ifndef SKY130_HILAS_NFETMIRRORPAIRS
`define SKY130_HILAS_NFETMIRRORPAIRS

/**
 * sky130_hilas_nFETmirrorPairs: pairs of nFET current mirrors
 *
 * Verilog wrapper for sky130_hilas_nFETmirrorPairs.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_nFETmirrorPairs (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_nFETmirrorPairs (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_NFETMIRRORPAIRS


//--------EOF---------

`ifndef SKY130_HILAS_DOUBLETGATE01
`define SKY130_HILAS_DOUBLETGATE01

/**
 * sky130_hilas_DoubleTGate01: 2x1 array of transmission gates
 *
 * Verilog wrapper for sky130_hilas_DoubleTGate01.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_DoubleTGate01 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_DoubleTGate01 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_DOUBLETGATE01


//--------EOF---------

`ifndef SKY130_HILAS_PFETDEVICE01BA
`define SKY130_HILAS_PFETDEVICE01BA

/**
 * sky130_hilas_pFETdevice01ba: pFET transistor used in DAC block
 *
 * Verilog wrapper for sky130_hilas_pFETdevice01ba.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_pFETdevice01ba (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_pFETdevice01ba (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_PFETDEVICE01BA


//--------EOF---------

`ifndef SKY130_HILAS_INVERT01
`define SKY130_HILAS_INVERT01

/**
 * sky130_hilas_invert01: None
 *
 * Verilog wrapper for sky130_hilas_invert01.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_invert01 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_invert01 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_INVERT01


//--------EOF---------

`ifndef SKY130_HILAS_FGHUGEVARACTORCAPACITOR01
`define SKY130_HILAS_FGHUGEVARACTORCAPACITOR01

/**
 * sky130_hilas_FGHugeVaractorCapacitor01: one large varactor cap
 *
 * Verilog wrapper for sky130_hilas_FGHugeVaractorCapacitor01.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_FGHugeVaractorCapacitor01 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_FGHugeVaractorCapacitor01 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_FGHUGEVARACTORCAPACITOR01


//--------EOF---------

`ifndef SKY130_HILAS_SWC4X1CELLOVERLAP
`define SKY130_HILAS_SWC4X1CELLOVERLAP

/**
 * sky130_hilas_swc4x1cellOverlap: 4x1 array of FG switch cell using overlap capacitors
 *
 * Verilog wrapper for sky130_hilas_swc4x1cellOverlap.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_swc4x1cellOverlap (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_swc4x1cellOverlap (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_SWC4X1CELLOVERLAP


//--------EOF---------

`ifndef SKY130_HILAS_PFETLARGEPART1
`define SKY130_HILAS_PFETLARGEPART1

/**
 * sky130_hilas_pFETLargePart1: Part of the W/L=100 pFET transistor
 *
 * Verilog wrapper for sky130_hilas_pFETLargePart1.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_pFETLargePart1 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_pFETLargePart1 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_PFETLARGEPART1


//--------EOF---------

`ifndef SKY130_HILAS_M22M4
`define SKY130_HILAS_M22M4

/**
 * sky130_hilas_m22m4: m2 to m4 contact
 *
 * Verilog wrapper for sky130_hilas_m22m4.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_m22m4 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_m22m4 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_M22M4


//--------EOF---------

`ifndef SKY130_HILAS_FGVARACTORTUNNELCAP01
`define SKY130_HILAS_FGVARACTORTUNNELCAP01

/**
 * sky130_hilas_FGVaractorTunnelCap01: Tunneling cpacitor using a standard varactor capacitor
 *
 * Verilog wrapper for sky130_hilas_FGVaractorTunnelCap01.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_FGVaractorTunnelCap01 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_FGVaractorTunnelCap01 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_FGVARACTORTUNNELCAP01


//--------EOF---------

`ifndef SKY130_HILAS_NFETLARGE
`define SKY130_HILAS_NFETLARGE

/**
 * sky130_hilas_nFETLarge: Single Large (W//L=100) nFET Transistor
 *
 * Verilog wrapper for sky130_hilas_nFETLarge.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_nFETLarge (
    GATE,
    SOURCE,
    DRAIN,
    VGND,
    VNB,
    VPB
);
        inout GATE;
        inout SOURCE;
        inout DRAIN;
        inout VGND;
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_nFETLarge (
    GATE,
    SOURCE,
    DRAIN
);
        inout GATE;
        inout SOURCE;
        inout DRAIN;
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_NFETLARGE


//--------EOF---------

`ifndef SKY130_HILAS_HORIZPCELL01
`define SKY130_HILAS_HORIZPCELL01

/**
 * sky130_hilas_horizPcell01: None
 *
 * Verilog wrapper for sky130_hilas_horizPcell01.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_horizPcell01 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_horizPcell01 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_HORIZPCELL01


//--------EOF---------

`ifndef SKY130_HILAS_PFETLARGE
`define SKY130_HILAS_PFETLARGE

/**
 * sky130_hilas_pFETLarge: Single Large (W/L=100) pFET Transistor
 *
 * Verilog wrapper for sky130_hilas_pFETLarge.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_pFETLarge (
    GATE,
    SOURCE,
    DRAIN,
    WELL,
    VNB,
    VPB
);
        inout GATE;
        inout SOURCE;
        inout DRAIN;
        inout WELL;
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_pFETLarge (
    GATE,
    SOURCE,
    DRAIN,
    WELL
);
        inout GATE;
        inout SOURCE;
        inout DRAIN;
        inout WELL;
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_PFETLARGE


//--------EOF---------

`ifndef SKY130_HILAS_POLYRESISTORGND
`define SKY130_HILAS_POLYRESISTORGND

/**
 * sky130_hilas_polyresistorGND: protective current-limiting resistor to ground
 *
 * Verilog wrapper for sky130_hilas_polyresistorGND.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_polyresistorGND (
    INPUT,
    OUTPUT,
    VGND,
    VNB,
    VPB
);
        inout INPUT;
        inout OUTPUT;
        inout VGND;
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_polyresistorGND (
    INPUT,
    OUTPUT
);
        inout INPUT;
        inout OUTPUT;
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_POLYRESISTORGND


//--------EOF---------

`ifndef SKY130_HILAS_WTASINGLESTAGE01
`define SKY130_HILAS_WTASINGLESTAGE01

/**
 * sky130_hilas_WTAsinglestage01: None
 *
 * Verilog wrapper for sky130_hilas_WTAsinglestage01.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_WTAsinglestage01 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_WTAsinglestage01 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_WTASINGLESTAGE01


//--------EOF---------

`ifndef SKY130_HILAS_LEVELSHIFT4INPUTUP
`define SKY130_HILAS_LEVELSHIFT4INPUTUP

/**
 * sky130_hilas_LevelShift4InputUp: 4-channel level shifter
 *
 * Verilog wrapper for sky130_hilas_LevelShift4InputUp.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_LevelShift4InputUp (
    VINJ,
    OUTPUT1,
    OUTPUT2,
    OUTPUT3,
    OUTPUT4,
    INPUT1,
    INPUT2,
    INPUT3,
    INPUT4,
    VPWR,
    VGND,
    VNB,
    VPB
);
        inout VINJ;
        inout OUTPUT1;
        inout OUTPUT2;
        inout OUTPUT3;
        inout OUTPUT4;
        inout INPUT1;
        inout INPUT2;
        inout INPUT3;
        inout INPUT4;
        inout VPWR;
        inout VGND;
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_LevelShift4InputUp (
    VINJ,
    OUTPUT1,
    OUTPUT2,
    OUTPUT3,
    OUTPUT4,
    INPUT1,
    INPUT2,
    INPUT3,
    INPUT4
);
        inout VINJ;
        inout OUTPUT1;
        inout OUTPUT2;
        inout OUTPUT3;
        inout OUTPUT4;
        inout INPUT1;
        inout INPUT2;
        inout INPUT3;
        inout INPUT4;
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_LEVELSHIFT4INPUTUP


//--------EOF---------

`ifndef SKY130_HILAS_NFETMED
`define SKY130_HILAS_NFETMED

/**
 * sky130_hilas_nFETmed: None
 *
 * Verilog wrapper for sky130_hilas_nFETmed.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_nFETmed (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_nFETmed (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_NFETMED


//--------EOF---------

`ifndef SKY130_HILAS_TACOREBLOCK
`define SKY130_HILAS_TACOREBLOCK

/**
 * sky130_hilas_TACoreBlock: None
 *
 * Verilog wrapper for sky130_hilas_TACoreBlock.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_TACoreBlock (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_TACoreBlock (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_TACOREBLOCK


//--------EOF---------

`ifndef SKY130_HILAS_SWC4X2CELL
`define SKY130_HILAS_SWC4X2CELL

/**
 * sky130_hilas_swc4x2cell: 4x2 array of FG switch cell, Varactor capacitor cell
 *
 * Verilog wrapper for sky130_hilas_swc4x2cell.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_swc4x2cell (
    DRAIN1,
    DRAIN2,
    DRAIN3,
    DRAIN4,
    GATE1,
    GATE2,
    GATESELECT1,
    GATESELECT2,
    ROW1,
    ROW2,
    ROW3,
    ROW4,
    VINJ,
    VTUN,
    VGND,
    VNB,
    VPB
);
        inout DRAIN1;
        inout DRAIN2;
        inout DRAIN3;
        inout DRAIN4;
        inout GATE1;
        inout GATE2;
        inout GATESELECT1;
        inout GATESELECT2;
        inout ROW1;
        inout ROW2;
        inout ROW3;
        inout ROW4;
        inout VINJ;
        inout VTUN;
        inout VGND;
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_swc4x2cell (
    DRAIN1,
    DRAIN2,
    DRAIN3,
    DRAIN4,
    GATE1,
    GATE2,
    GATESELECT1,
    GATESELECT2,
    ROW1,
    ROW2,
    ROW3,
    ROW4,
    VINJ,
    VTUN
);
        inout DRAIN1;
        inout DRAIN2;
        inout DRAIN3;
        inout DRAIN4;
        inout GATE1;
        inout GATE2;
        inout GATESELECT1;
        inout GATESELECT2;
        inout ROW1;
        inout ROW2;
        inout ROW3;
        inout ROW4;
        inout VINJ;
        inout VTUN;
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_SWC4X2CELL


//--------EOF---------

`ifndef SKY130_HILAS_TRANS4SMALL
`define SKY130_HILAS_TRANS4SMALL

/**
 * sky130_hilas_Trans4small: 3 small nFETs + 3 small pFETs
 *
 * Verilog wrapper for sky130_hilas_Trans4small.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_Trans4small (
    NFET_SOURCE1,
    NFET_GATE1,
    NFET_SOURCE2,
    NFET_GATE2,
    NFET_SOURCE3,
    NFET_GATE3,
    PFET_SOURCE1,
    PFET_GATE1,
    PFET_SOURCE2,
    PFET_GATE2,
    PFET_SOURCE3,
    PFET_GATE3,
    WELL,
    PFET_DRAIN3,
    PFET_DRAIN2,
    PFET_DRAIN1,
    NFET_DRAIN3,
    NFET_DRAIN2,
    NFET_DRAIN1,
    VGND,
    VNB,
    VPB
);
        inout NFET_SOURCE1;
        inout NFET_GATE1;
        inout NFET_SOURCE2;
        inout NFET_GATE2;
        inout NFET_SOURCE3;
        inout NFET_GATE3;
        inout PFET_SOURCE1;
        inout PFET_GATE1;
        inout PFET_SOURCE2;
        inout PFET_GATE2;
        inout PFET_SOURCE3;
        inout PFET_GATE3;
        inout WELL;
        inout PFET_DRAIN3;
        inout PFET_DRAIN2;
        inout PFET_DRAIN1;
        inout NFET_DRAIN3;
        inout NFET_DRAIN2;
        inout NFET_DRAIN1;
        inout VGND;
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_Trans4small (
    NFET_SOURCE1,
    NFET_GATE1,
    NFET_SOURCE2,
    NFET_GATE2,
    NFET_SOURCE3,
    NFET_GATE3,
    PFET_SOURCE1,
    PFET_GATE1,
    PFET_SOURCE2,
    PFET_GATE2,
    PFET_SOURCE3,
    PFET_GATE3,
    WELL,
    PFET_DRAIN3,
    PFET_DRAIN2,
    PFET_DRAIN1,
    NFET_DRAIN3,
    NFET_DRAIN2,
    NFET_DRAIN1
);
        inout NFET_SOURCE1;
        inout NFET_GATE1;
        inout NFET_SOURCE2;
        inout NFET_GATE2;
        inout NFET_SOURCE3;
        inout NFET_GATE3;
        inout PFET_SOURCE1;
        inout PFET_GATE1;
        inout PFET_SOURCE2;
        inout PFET_GATE2;
        inout PFET_SOURCE3;
        inout PFET_GATE3;
        inout WELL;
        inout PFET_DRAIN3;
        inout PFET_DRAIN2;
        inout PFET_DRAIN1;
        inout NFET_DRAIN3;
        inout NFET_DRAIN2;
        inout NFET_DRAIN1;
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_TRANS4SMALL


//--------EOF---------

`ifndef SKY130_HILAS_DRAINSELECT01
`define SKY130_HILAS_DRAINSELECT01

/**
 * sky130_hilas_drainSelect01: multiplexor for drain selection for 4 drain lines, pitch matched
 *
 * Verilog wrapper for sky130_hilas_drainSelect01.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_drainSelect01 (
    DRAIN3,
    VINJ,
    DRAIN_MUX,
    SELECT2,
    SELECT1,
    SELECT3,
    SELECT4,
    VGND,
    VNB,
    VPB
);
        inout DRAIN3;
        inout VINJ;
        inout DRAIN_MUX;
        inout SELECT2;
        inout SELECT1;
        inout SELECT3;
        inout SELECT4;
        inout VGND;
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_drainSelect01 (
    DRAIN3,
    VINJ,
    DRAIN_MUX,
    SELECT2,
    SELECT1,
    SELECT3,
    SELECT4
);
        inout DRAIN3;
        inout VINJ;
        inout DRAIN_MUX;
        inout SELECT2;
        inout SELECT1;
        inout SELECT3;
        inout SELECT4;
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_DRAINSELECT01


//--------EOF---------

`ifndef SKY130_HILAS_CAPMODULE01
`define SKY130_HILAS_CAPMODULE01

/**
 * sky130_hilas_CapModule01: None
 *
 * Verilog wrapper for sky130_hilas_CapModule01.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_CapModule01 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_CapModule01 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_CAPMODULE01


//--------EOF---------

`ifndef SKY130_HILAS_LEFTPROTECTION
`define SKY130_HILAS_LEFTPROTECTION

/**
 * sky130_hilas_LeftProtection: 
 *
 * Verilog wrapper for sky130_hilas_LeftProtection.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_LeftProtection (
    IO25,
    IO26,
    IO27,
    IO28,
    IO29,
    IO30,
    IO31,
    IO32,
    IO33,
    IO34,
    IO35,
    IO36,
    IO37,
    PIN1,
    PIN2,
    PIN4,
    PIN5,
    PIN6,
    PIN7,
    PIN8,
    PIN9,
    PIN10,
    PIN11,
    PIN12,
    PIN13,
    VNB,
    VPB
);
        inout IO25;
        inout IO26;
        inout IO27;
        inout IO28;
        inout IO29;
        inout IO30;
        inout IO31;
        inout IO32;
        inout IO33;
        inout IO34;
        inout IO35;
        inout IO36;
        inout IO37;
        inout PIN1;
        inout PIN2;
        inout PIN4;
        inout PIN5;
        inout PIN6;
        inout PIN7;
        inout PIN8;
        inout PIN9;
        inout PIN10;
        inout PIN11;
        inout PIN12;
        inout PIN13;
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_LeftProtection (
    IO25,
    IO26,
    IO27,
    IO28,
    IO29,
    IO30,
    IO31,
    IO32,
    IO33,
    IO34,
    IO35,
    IO36,
    IO37,
    PIN1,
    PIN2,
    PIN4,
    PIN5,
    PIN6,
    PIN7,
    PIN8,
    PIN9,
    PIN10,
    PIN11,
    PIN12,
    PIN13
);
        inout IO25;
        inout IO26;
        inout IO27;
        inout IO28;
        inout IO29;
        inout IO30;
        inout IO31;
        inout IO32;
        inout IO33;
        inout IO34;
        inout IO35;
        inout IO36;
        inout IO37;
        inout PIN1;
        inout PIN2;
        inout PIN4;
        inout PIN5;
        inout PIN6;
        inout PIN7;
        inout PIN8;
        inout PIN9;
        inout PIN10;
        inout PIN11;
        inout PIN12;
        inout PIN13;
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_LEFTPROTECTION


//--------EOF---------

`ifndef SKY130_HILAS_FGVARACTORCAPACITOR02
`define SKY130_HILAS_FGVARACTORCAPACITOR02

/**
 * sky130_hilas_FGVaractorCapacitor02: variant 2, varactor cap for floating-gate charge storage
 *
 * Verilog wrapper for sky130_hilas_FGVaractorCapacitor02.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_FGVaractorCapacitor02 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_FGVaractorCapacitor02 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_FGVARACTORCAPACITOR02


//--------EOF---------

`ifndef SKY130_HILAS_TGATESINGLE01PART1
`define SKY130_HILAS_TGATESINGLE01PART1

/**
 * sky130_hilas_TgateSingle01Part1: None
 *
 * Verilog wrapper for sky130_hilas_TgateSingle01Part1.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_TgateSingle01Part1 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_TgateSingle01Part1 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_TGATESINGLE01PART1


//--------EOF---------

`ifndef SKY130_HILAS_RIGHTPROTECTION
`define SKY130_HILAS_RIGHTPROTECTION

/**
 * sky130_hilas_RightProtection: 
 *
 * Verilog wrapper for sky130_hilas_RightProtection.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_RightProtection (
    IO7,
    IO8,
    IO9,
    IO10,
    IO11,
    IO13,
    IO12,
    PIN1,
    PIN2,
    PIN3,
    PIN4,
    PIN5,
    PIN6,
    PIN7,
    VNB,
    VPB
);
        inout IO7;
        inout IO8;
        inout IO9;
        inout IO10;
        inout IO11;
        inout IO13;
        inout IO12;
        inout PIN1;
        inout PIN2;
        inout PIN3;
        inout PIN4;
        inout PIN5;
        inout PIN6;
        inout PIN7;
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_RightProtection (
    IO7,
    IO8,
    IO9,
    IO10,
    IO11,
    IO13,
    IO12,
    PIN1,
    PIN2,
    PIN3,
    PIN4,
    PIN5,
    PIN6,
    PIN7
);
        inout IO7;
        inout IO8;
        inout IO9;
        inout IO10;
        inout IO11;
        inout IO13;
        inout IO12;
        inout PIN1;
        inout PIN2;
        inout PIN3;
        inout PIN4;
        inout PIN5;
        inout PIN6;
        inout PIN7;
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_RIGHTPROTECTION


//--------EOF---------

`ifndef SKY130_HILAS_VINJINV2
`define SKY130_HILAS_VINJINV2

/**
 * sky130_hilas_VinjInv2: logical inverter for VINJ-level voltages
 *
 * Verilog wrapper for sky130_hilas_VinjInv2.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_VinjInv2 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_VinjInv2 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_VINJINV2


//--------EOF---------

`ifndef SKY130_HILAS_CAPMODULE02
`define SKY130_HILAS_CAPMODULE02

/**
 * sky130_hilas_CapModule02: None
 *
 * Verilog wrapper for sky130_hilas_CapModule02.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_CapModule02 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_CapModule02 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_CAPMODULE02


//--------EOF---------

`ifndef SKY130_HILAS_DAC6TRANSISTORSTACK01C
`define SKY130_HILAS_DAC6TRANSISTORSTACK01C

/**
 * sky130_hilas_DAC6TransistorStack01c: None
 *
 * Verilog wrapper for sky130_hilas_DAC6TransistorStack01c.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_DAC6TransistorStack01c (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_DAC6TransistorStack01c (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_DAC6TRANSISTORSTACK01C


//--------EOF---------

`ifndef SKY130_HILAS_FGCHARACTERIZATION01
`define SKY130_HILAS_FGCHARACTERIZATION01

/**
 * sky130_hilas_FGcharacterization01: FG test strucure that uses a capacitor around a transconductance amplifier
 *
 * Verilog wrapper for sky130_hilas_FGcharacterization01.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_FGcharacterization01 (
    VTUN,
    GATE1,
    GATE3,
    VTUNOVERLAP01,
    GATE2,
    GATE4,
    LARGECAPACITOR,
    VINJ,
    OUTPUT,
    VREF,
    VBIAS,
    DRAIN1,
    SOURCE1,
    VGND,
    VNB,
    VPB
);
        inout VTUN;
        inout GATE1;
        inout GATE3;
        inout VTUNOVERLAP01;
        inout GATE2;
        inout GATE4;
        inout LARGECAPACITOR;
        inout VINJ;
        inout OUTPUT;
        inout VREF;
        inout VBIAS;
        inout DRAIN1;
        inout SOURCE1;
        inout VGND;
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_FGcharacterization01 (
    VTUN,
    GATE1,
    GATE3,
    VTUNOVERLAP01,
    GATE2,
    GATE4,
    LARGECAPACITOR,
    VINJ,
    OUTPUT,
    VREF,
    VBIAS,
    DRAIN1,
    SOURCE1
);
        inout VTUN;
        inout GATE1;
        inout GATE3;
        inout VTUNOVERLAP01;
        inout GATE2;
        inout GATE4;
        inout LARGECAPACITOR;
        inout VINJ;
        inout OUTPUT;
        inout VREF;
        inout VBIAS;
        inout DRAIN1;
        inout SOURCE1;
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_FGCHARACTERIZATION01


//--------EOF---------

`ifndef SKY130_HILAS_OVERLAPCAP01
`define SKY130_HILAS_OVERLAPCAP01

/**
 * sky130_hilas_overlapCap01: overlap capacitor based capacitor
 *
 * Verilog wrapper for sky130_hilas_overlapCap01.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_overlapCap01 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_overlapCap01 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_OVERLAPCAP01


//--------EOF---------

`ifndef SKY130_HILAS_PTRANSISTORPAIR
`define SKY130_HILAS_PTRANSISTORPAIR

/**
 * sky130_hilas_pTransistorPair: None
 *
 * Verilog wrapper for sky130_hilas_pTransistorPair.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_pTransistorPair (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_pTransistorPair (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_PTRANSISTORPAIR


//--------EOF---------

`ifndef SKY130_HILAS_CELLATTEMPT01
`define SKY130_HILAS_CELLATTEMPT01

/**
 * sky130_hilas_cellAttempt01: 4x1 array of FG switch cell, Varactor capacitor cell
 *
 * Verilog wrapper for sky130_hilas_cellAttempt01.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_cellAttempt01 (
    VTUN,
    VINJ,
    COLSEL1,
    GATE1,
    ROW4,
    DRAIN4,
    DRAIN1,
    ROW1,
    ROW3,
    DRAIN3,
    DRAIN2,
    ROW2,
    VGND,
    VNB,
    VPB
);
        inout VTUN;
        inout VINJ;
        inout COLSEL1;
        inout GATE1;
        inout ROW4;
        inout DRAIN4;
        inout DRAIN1;
        inout ROW1;
        inout ROW3;
        inout DRAIN3;
        inout DRAIN2;
        inout ROW2;
        inout VGND;
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_cellAttempt01 (
    VTUN,
    VINJ,
    COLSEL1,
    GATE1,
    ROW4,
    DRAIN4,
    DRAIN1,
    ROW1,
    ROW3,
    DRAIN3,
    DRAIN2,
    ROW2
);
        inout VTUN;
        inout VINJ;
        inout COLSEL1;
        inout GATE1;
        inout ROW4;
        inout DRAIN4;
        inout DRAIN1;
        inout ROW1;
        inout ROW3;
        inout DRAIN3;
        inout DRAIN2;
        inout ROW2;
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_CELLATTEMPT01


//--------EOF---------

`ifndef SKY130_HILAS_POLY2M1
`define SKY130_HILAS_POLY2M1

/**
 * sky130_hilas_poly2m1: polysilicon layer to m1 contact
 *
 * Verilog wrapper for sky130_hilas_poly2m1.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_poly2m1 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_poly2m1 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_POLY2M1


//--------EOF---------

`ifndef SKY130_HILAS_PFETDEVICE01W1
`define SKY130_HILAS_PFETDEVICE01W1

/**
 * sky130_hilas_pFETdevice01w1: 
 *
 * Verilog wrapper for sky130_hilas_pFETdevice01w1.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_pFETdevice01w1 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_pFETdevice01w1 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_PFETDEVICE01W1


//--------EOF---------

`ifndef SKY130_HILAS_DAC5BIT01
`define SKY130_HILAS_DAC5BIT01

/**
 * sky130_hilas_DAC5bit01: 5-bit digital-to-analog converter (under 6.05um at the moment; thinking through expansion to 6bit and 7bit, and they would use this cell
 *
 * Verilog wrapper for sky130_hilas_DAC5bit01.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_DAC5bit01 (
    A0,
    A1,
    A2,
    A3,
    A4,
    OUT,
    VPWR,
    VNB,
    VPB
);
        inout A0;
        inout A1;
        inout A2;
        inout A3;
        inout A4;
        inout OUT;
        inout VPWR;
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_DAC5bit01 (
    A0,
    A1,
    A2,
    A3,
    A4,
    OUT
);
        inout A0;
        inout A1;
        inout A2;
        inout A3;
        inout A4;
        inout OUT;
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_DAC5BIT01


//--------EOF---------

`ifndef SKY130_HILAS_VINJNOR3
`define SKY130_HILAS_VINJNOR3

/**
 * sky130_hilas_VinjNOR3: 3-input NOR gate capable of VING voltage
 *
 * Verilog wrapper for sky130_hilas_VinjNOR3.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_VinjNOR3 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_VinjNOR3 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_VINJNOR3


//--------EOF---------

`ifndef SKY130_HILAS_VINJDECODE2TO4
`define SKY130_HILAS_VINJDECODE2TO4

/**
 * sky130_hilas_VinjDecode2to4: a 2-to-4 decoder capable of handling VINJ voltage
 *
 * Verilog wrapper for sky130_hilas_VinjDecode2to4.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_VinjDecode2to4 (
    OUTPUT00,
    OUTPUT01,
    OUTPUT10,
    OUTPUT11,
    VINJ,
    IN2,
    IN1,
    ENABLE,
    VGND,
    VNB,
    VPB
);
        inout OUTPUT00;
        inout OUTPUT01;
        inout OUTPUT10;
        inout OUTPUT11;
        inout VINJ;
        inout IN2;
        inout IN1;
        inout ENABLE;
        inout VGND;
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_VinjDecode2to4 (
    OUTPUT00,
    OUTPUT01,
    OUTPUT10,
    OUTPUT11,
    VINJ,
    IN2,
    IN1,
    ENABLE
);
        inout OUTPUT00;
        inout OUTPUT01;
        inout OUTPUT10;
        inout OUTPUT11;
        inout VINJ;
        inout IN2;
        inout IN1;
        inout ENABLE;
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_VINJDECODE2TO4


//--------EOF---------

`ifndef SKY130_HILAS_PFETDEVICE01AA
`define SKY130_HILAS_PFETDEVICE01AA

/**
 * sky130_hilas_pFETdevice01aa: pFET transistor used in DAC block
 *
 * Verilog wrapper for sky130_hilas_pFETdevice01aa.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_pFETdevice01aa (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_pFETdevice01aa (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_PFETDEVICE01AA


//--------EOF---------

`ifndef SKY130_HILAS_NDIFFTHOXCONTACT
`define SKY130_HILAS_NDIFFTHOXCONTACT

/**
 * sky130_hilas_nDiffThOxContact: None
 *
 * Verilog wrapper for sky130_hilas_nDiffThOxContact.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_nDiffThOxContact (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_nDiffThOxContact (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_NDIFFTHOXCONTACT


//--------EOF---------

`ifndef SKY130_HILAS_WELLCONTACT
`define SKY130_HILAS_WELLCONTACT

/**
 * sky130_hilas_wellContact: contact to a well block, typically used for contacting tunneling junctions in a well.
 *
 * Verilog wrapper for sky130_hilas_wellContact.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_wellContact (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_wellContact (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_WELLCONTACT


//--------EOF---------

`ifndef SKY130_HILAS_OVERLAPCAP02
`define SKY130_HILAS_OVERLAPCAP02

/**
 * sky130_hilas_overlapCap02: overlap capacitor based capacitor)
 *
 * Verilog wrapper for sky130_hilas_overlapCap02.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_overlapCap02 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_overlapCap02 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_OVERLAPCAP02


//--------EOF---------

`ifndef SKY130_HILAS_PFETDEVICE01C
`define SKY130_HILAS_PFETDEVICE01C

/**
 * sky130_hilas_pFETdevice01c: pFET transistor used in DAC block
 *
 * Verilog wrapper for sky130_hilas_pFETdevice01c.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_pFETdevice01c (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_pFETdevice01c (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_PFETDEVICE01C


//--------EOF---------

`ifndef SKY130_HILAS_CAPACITORSIZE04
`define SKY130_HILAS_CAPACITORSIZE04

/**
 * sky130_hilas_capacitorSize04: large cap
 *
 * Verilog wrapper for sky130_hilas_capacitorSize04.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_capacitorSize04 (
    CAP1TERM02,
    CAP2TERM02,
    CAP2TERM01,
    CAP1TERM01,
    VNB,
    VPB
);
        inout CAP1TERM02;
        inout CAP2TERM02;
        inout CAP2TERM01;
        inout CAP1TERM01;
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_capacitorSize04 (
    CAP1TERM02,
    CAP2TERM02,
    CAP2TERM01,
    CAP1TERM01
);
        inout CAP1TERM02;
        inout CAP2TERM02;
        inout CAP2TERM01;
        inout CAP1TERM01;
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_CAPACITORSIZE04


//--------EOF---------

`ifndef SKY130_HILAS_SWC4X1CELLOVERLAP2
`define SKY130_HILAS_SWC4X1CELLOVERLAP2

/**
 * sky130_hilas_swc4x1cellOverlap2: 4x1 analog mux with overlap
 *
 * Verilog wrapper for sky130_hilas_swc4x1cellOverlap2.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_swc4x1cellOverlap2 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_swc4x1cellOverlap2 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_SWC4X1CELLOVERLAP2


//--------EOF---------

`ifndef SKY130_HILAS_HORIZTRANSCELL01A
`define SKY130_HILAS_HORIZTRANSCELL01A

/**
 * sky130_hilas_horizTransCell01a: 
 *
 * Verilog wrapper for sky130_hilas_horizTransCell01a.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_horizTransCell01a (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_horizTransCell01a (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_HORIZTRANSCELL01A


//--------EOF---------

`ifndef SKY130_HILAS_TA2CELL_NOFG
`define SKY130_HILAS_TA2CELL_NOFG

/**
 * sky130_hilas_TA2Cell_NoFG: Two transimpedane amplifiers with no floating-gate inputs.
 *
 * Verilog wrapper for sky130_hilas_TA2Cell_NoFG.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_TA2Cell_NoFG (
    COLSEL1,
    VIN12,
    VIN21,
    VIN22,
    OUTPUT1,
    OUTPUT2,
    DRAIN1,
    DRAIN2,
    VTUN,
    GATE1,
    VINJ,
    VIN11,
    VGND,
    VPWR,
    VNB,
    VPB
);
        inout COLSEL1;
        inout VIN12;
        inout VIN21;
        inout VIN22;
        inout OUTPUT1;
        inout OUTPUT2;
        inout DRAIN1;
        inout DRAIN2;
        inout VTUN;
        inout GATE1;
        inout VINJ;
        inout VIN11;
        inout VGND;
        inout VPWR;
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_TA2Cell_NoFG (
    COLSEL1,
    VIN12,
    VIN21,
    VIN22,
    OUTPUT1,
    OUTPUT2,
    DRAIN1,
    DRAIN2,
    VTUN,
    GATE1,
    VINJ,
    VIN11
);
        inout COLSEL1;
        inout VIN12;
        inout VIN21;
        inout VIN22;
        inout OUTPUT1;
        inout OUTPUT2;
        inout DRAIN1;
        inout DRAIN2;
        inout VTUN;
        inout GATE1;
        inout VINJ;
        inout VIN11;
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_TA2CELL_NOFG


//--------EOF---------

`ifndef SKY130_HILAS_FGBIAS2X1CELL
`define SKY130_HILAS_FGBIAS2X1CELL

/**
 * sky130_hilas_FGBias2x1cell: None
 *
 * Verilog wrapper for sky130_hilas_FGBias2x1cell.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_FGBias2x1cell (
    DRAIN1,
    DRAIN4,
    GATECOL,
    GATE_CONTROL,
    OUTPUT1,
    OUTPUT2,
    VINJ,
    VTUN,
    VGND,
    VNB,
    VPB
);
        inout DRAIN1;
        inout DRAIN4;
        inout GATECOL;
        inout GATE_CONTROL;
        inout OUTPUT1;
        inout OUTPUT2;
        inout VINJ;
        inout VTUN;
        inout VGND;
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_FGBias2x1cell (
    DRAIN1,
    DRAIN4,
    GATECOL,
    GATE_CONTROL,
    OUTPUT1,
    OUTPUT2,
    VINJ,
    VTUN
);
        inout DRAIN1;
        inout DRAIN4;
        inout GATECOL;
        inout GATE_CONTROL;
        inout OUTPUT1;
        inout OUTPUT2;
        inout VINJ;
        inout VTUN;
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_FGBIAS2X1CELL


//--------EOF---------

`ifndef SKY130_HILAS_CAPMODULE03
`define SKY130_HILAS_CAPMODULE03

/**
 * sky130_hilas_CapModule03: None
 *
 * Verilog wrapper for sky130_hilas_CapModule03.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_CapModule03 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_CapModule03 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_CAPMODULE03


//--------EOF---------

`ifndef SKY130_HILAS_PFETMIRROR02
`define SKY130_HILAS_PFETMIRROR02

/**
 * sky130_hilas_pFETmirror02: second pFET current mirror
 *
 * Verilog wrapper for sky130_hilas_pFETmirror02.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_pFETmirror02 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_pFETmirror02 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_PFETMIRROR02


//--------EOF---------

`ifndef SKY130_HILAS_NFETMIRRORPAIRS2
`define SKY130_HILAS_NFETMIRRORPAIRS2

/**
 * sky130_hilas_nFETmirrorPairs2: None
 *
 * Verilog wrapper for sky130_hilas_nFETmirrorPairs2.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_nFETmirrorPairs2 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_nFETmirrorPairs2 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_NFETMIRRORPAIRS2


//--------EOF---------

`ifndef SKY130_HILAS_TOPPROTECTION
`define SKY130_HILAS_TOPPROTECTION

/**
 * sky130_hilas_TopProtection: 
 *
 * Verilog wrapper for sky130_hilas_TopProtection.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_TopProtection (
    ANALOG00,
    ANALOG01,
    ANALOG02,
    ANALOG03,
    ANALOG04,
    ANALOG05,
    ANALOG06,
    ANALOG07,
    ANALOG08,
    ANALOG09,
    ANALOG10,
    PIN1,
    PIN2,
    PIN3,
    PIN4,
    PIN5,
    PIN6,
    PIN7,
    PIN8,
    PIN9,
    PIN10,
    VTUN,
    VNB,
    VPB
);
        inout ANALOG00;
        inout ANALOG01;
        inout ANALOG02;
        inout ANALOG03;
        inout ANALOG04;
        inout ANALOG05;
        inout ANALOG06;
        inout ANALOG07;
        inout ANALOG08;
        inout ANALOG09;
        inout ANALOG10;
        inout PIN1;
        inout PIN2;
        inout PIN3;
        inout PIN4;
        inout PIN5;
        inout PIN6;
        inout PIN7;
        inout PIN8;
        inout PIN9;
        inout PIN10;
        inout VTUN;
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_TopProtection (
    ANALOG00,
    ANALOG01,
    ANALOG02,
    ANALOG03,
    ANALOG04,
    ANALOG05,
    ANALOG06,
    ANALOG07,
    ANALOG08,
    ANALOG09,
    ANALOG10,
    PIN1,
    PIN2,
    PIN3,
    PIN4,
    PIN5,
    PIN6,
    PIN7,
    PIN8,
    PIN9,
    PIN10,
    VTUN
);
        inout ANALOG00;
        inout ANALOG01;
        inout ANALOG02;
        inout ANALOG03;
        inout ANALOG04;
        inout ANALOG05;
        inout ANALOG06;
        inout ANALOG07;
        inout ANALOG08;
        inout ANALOG09;
        inout ANALOG10;
        inout PIN1;
        inout PIN2;
        inout PIN3;
        inout PIN4;
        inout PIN5;
        inout PIN6;
        inout PIN7;
        inout PIN8;
        inout PIN9;
        inout PIN10;
        inout VTUN;
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_TOPPROTECTION


//--------EOF---------

`ifndef SKY130_HILAS_TGATE4SINGLE01
`define SKY130_HILAS_TGATE4SINGLE01

/**
 * sky130_hilas_Tgate4Single01: 4 single-throw transmission gates
 *
 * Verilog wrapper for sky130_hilas_Tgate4Single01.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_Tgate4Single01 (
    INPUT1_2,
    SELECT2,
    OUTPUT2,
    OUTPUT4,
    OUTPUT3,
    OUTPUT1,
    INPUT1_4,
    SELECT4,
    SELECT3,
    INPUT1_3,
    SELECT1,
    INPUT1_1,
    VPWR,
    VGND,
    VNB,
    VPB
);
        inout INPUT1_2;
        inout SELECT2;
        inout OUTPUT2;
        inout OUTPUT4;
        inout OUTPUT3;
        inout OUTPUT1;
        inout INPUT1_4;
        inout SELECT4;
        inout SELECT3;
        inout INPUT1_3;
        inout SELECT1;
        inout INPUT1_1;
        inout VPWR;
        inout VGND;
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_Tgate4Single01 (
    INPUT1_2,
    SELECT2,
    OUTPUT2,
    OUTPUT4,
    OUTPUT3,
    OUTPUT1,
    INPUT1_4,
    SELECT4,
    SELECT3,
    INPUT1_3,
    SELECT1,
    INPUT1_1
);
        inout INPUT1_2;
        inout SELECT2;
        inout OUTPUT2;
        inout OUTPUT4;
        inout OUTPUT3;
        inout OUTPUT1;
        inout INPUT1_4;
        inout SELECT4;
        inout SELECT3;
        inout INPUT1_3;
        inout SELECT1;
        inout INPUT1_1;
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_TGATE4SINGLE01


//--------EOF---------

`ifndef SKY130_HILAS_OVERLAPCAP02A
`define SKY130_HILAS_OVERLAPCAP02A

/**
 * sky130_hilas_overlapCap02a: overlap capacitor based capacitor
 *
 * Verilog wrapper for sky130_hilas_overlapCap02a.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_overlapCap02a (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_overlapCap02a (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_OVERLAPCAP02A


//--------EOF---------

`ifndef SKY130_HILAS_SWC4X1BIASCELL
`define SKY130_HILAS_SWC4X1BIASCELL

/**
 * sky130_hilas_swc4x1BiasCell: 4x1 array of FG switch cell configured pFET as current sources
 *
 * Verilog wrapper for sky130_hilas_swc4x1BiasCell.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_swc4x1BiasCell (
    ROW1,
    ROW2,
    ROW3,
    ROW4,
    VTUN,
    GATE1,
    VINJ,
    DRAIN3,
    DRAIN4,
    DRAIN1,
    DRAIN2,
    VPWR,
    VGND,
    VNB,
    VPB
);
        inout ROW1;
        inout ROW2;
        inout ROW3;
        inout ROW4;
        inout VTUN;
        inout GATE1;
        inout VINJ;
        inout DRAIN3;
        inout DRAIN4;
        inout DRAIN1;
        inout DRAIN2;
        inout VPWR;
        inout VGND;
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_swc4x1BiasCell (
    ROW1,
    ROW2,
    ROW3,
    ROW4,
    VTUN,
    GATE1,
    VINJ,
    DRAIN3,
    DRAIN4,
    DRAIN1,
    DRAIN2
);
        inout ROW1;
        inout ROW2;
        inout ROW3;
        inout ROW4;
        inout VTUN;
        inout GATE1;
        inout VINJ;
        inout DRAIN3;
        inout DRAIN4;
        inout DRAIN1;
        inout DRAIN2;
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_SWC4X1BIASCELL


//--------EOF---------

`ifndef SKY130_HILAS_CAPACITORSIZE03
`define SKY130_HILAS_CAPACITORSIZE03

/**
 * sky130_hilas_capacitorSize03: mid-large cap
 *
 * Verilog wrapper for sky130_hilas_capacitorSize03.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_capacitorSize03 (
    CAPTERM02,
    CAPTERM01,
    VNB,
    VPB
);
        inout CAPTERM02;
        inout CAPTERM01;
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_capacitorSize03 (
    CAPTERM02,
    CAPTERM01
);
        inout CAPTERM02;
        inout CAPTERM01;
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_CAPACITORSIZE03


//--------EOF---------

`ifndef SKY130_HILAS_FGTRANS2X1CELL
`define SKY130_HILAS_FGTRANS2X1CELL

/**
 * sky130_hilas_FGtrans2x1cell: None
 *
 * Verilog wrapper for sky130_hilas_FGtrans2x1cell.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_FGtrans2x1cell (
    COLSEL1,
    VINJ,
    DRAIN1,
    DRAIN2,
    PROG,
    RUN,
    VIN2,
    VIN1,
    GATE1,
    VTUN,
    COL1,
    ROW1,
    ROW2,
    VGND,
    VNB,
    VPB
);
        inout COLSEL1;
        inout VINJ;
        inout DRAIN1;
        inout DRAIN2;
        inout PROG;
        inout RUN;
        inout VIN2;
        inout VIN1;
        inout GATE1;
        inout VTUN;
        inout COL1;
        inout ROW1;
        inout ROW2;
        inout VGND;
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_FGtrans2x1cell (
    COLSEL1,
    VINJ,
    DRAIN1,
    DRAIN2,
    PROG,
    RUN,
    VIN2,
    VIN1,
    GATE1,
    VTUN,
    COL1,
    ROW1,
    ROW2
);
        inout COLSEL1;
        inout VINJ;
        inout DRAIN1;
        inout DRAIN2;
        inout PROG;
        inout RUN;
        inout VIN2;
        inout VIN1;
        inout GATE1;
        inout VTUN;
        inout COL1;
        inout ROW1;
        inout ROW2;
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_FGTRANS2X1CELL


//--------EOF---------

`ifndef SKY130_HILAS_POLY2M2
`define SKY130_HILAS_POLY2M2

/**
 * sky130_hilas_poly2m2: polysilicon layer to m2 contact
 *
 * Verilog wrapper for sky130_hilas_poly2m2.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_poly2m2 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_poly2m2 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_POLY2M2


//--------EOF---------

`ifndef SKY130_HILAS_CAPMODULE01A
`define SKY130_HILAS_CAPMODULE01A

/**
 * sky130_hilas_CapModule01a: primitive cap, variant 01a
 *
 * Verilog wrapper for sky130_hilas_CapModule01a.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_CapModule01a (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_CapModule01a (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_CAPMODULE01A


//--------EOF---------

`ifndef SKY130_HILAS_PFETDEVICE01D
`define SKY130_HILAS_PFETDEVICE01D

/**
 * sky130_hilas_pFETdevice01d: pFET transistor used in DAC block
 *
 * Verilog wrapper for sky130_hilas_pFETdevice01d.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_pFETdevice01d (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_pFETdevice01d (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_PFETDEVICE01D


//--------EOF---------

`ifndef SKY130_HILAS_WTA4STAGE01
`define SKY130_HILAS_WTA4STAGE01

/**
 * sky130_hilas_WTA4Stage01: 4-input winner-take-all circuit. Connects directly to array of swc4x2cell. Can array vertically. Needs one nFET transistor current source.
 *
 * Verilog wrapper for sky130_hilas_WTA4Stage01.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_WTA4Stage01 (
    OUTPUT1,
    OUTPUT2,
    OUTPUT3,
    OUTPUT4,
    INPUT1,
    INPUT2,
    INPUT3,
    INPUT4,
    DRAIN1,
    GATE1,
    VTUN,
    WTAMIDDLENODE,
    COLSEL1,
    VINJ,
    DRAIN2,
    DRAIN3,
    DRAIN4,
    VGND,
    VNB,
    VPB
);
        inout OUTPUT1;
        inout OUTPUT2;
        inout OUTPUT3;
        inout OUTPUT4;
        inout INPUT1;
        inout INPUT2;
        inout INPUT3;
        inout INPUT4;
        inout DRAIN1;
        inout GATE1;
        inout VTUN;
        inout WTAMIDDLENODE;
        inout COLSEL1;
        inout VINJ;
        inout DRAIN2;
        inout DRAIN3;
        inout DRAIN4;
        inout VGND;
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_WTA4Stage01 (
    OUTPUT1,
    OUTPUT2,
    OUTPUT3,
    OUTPUT4,
    INPUT1,
    INPUT2,
    INPUT3,
    INPUT4,
    DRAIN1,
    GATE1,
    VTUN,
    WTAMIDDLENODE,
    COLSEL1,
    VINJ,
    DRAIN2,
    DRAIN3,
    DRAIN4
);
        inout OUTPUT1;
        inout OUTPUT2;
        inout OUTPUT3;
        inout OUTPUT4;
        inout INPUT1;
        inout INPUT2;
        inout INPUT3;
        inout INPUT4;
        inout DRAIN1;
        inout GATE1;
        inout VTUN;
        inout WTAMIDDLENODE;
        inout COLSEL1;
        inout VINJ;
        inout DRAIN2;
        inout DRAIN3;
        inout DRAIN4;
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_WTA4STAGE01


//--------EOF---------

`ifndef SKY130_HILAS_WTABLOCKSAMPLE01
`define SKY130_HILAS_WTABLOCKSAMPLE01

/**
 * sky130_hilas_WTAblockSample01: None
 *
 * Verilog wrapper for sky130_hilas_WTAblockSample01.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_WTAblockSample01 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_WTAblockSample01 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_WTABLOCKSAMPLE01


//--------EOF---------

`ifndef SKY130_HILAS_TOPPROTECTSTRUCTURE
`define SKY130_HILAS_TOPPROTECTSTRUCTURE

/**
 * sky130_hilas_TopProtectStructure: top level test structure with protection (duplicate of TopLevelProtectStructure)
 *
 * Verilog wrapper for sky130_hilas_TopProtectStructure.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_TopProtectStructure (
    IO07,
    IO08,
    IO09,
    IO10,
    IO11,
    IO12,
    IO13,
    IO25,
    IO26,
    IO27,
    IO28,
    IO29,
    IO30,
    IO31,
    IO32,
    IO33,
    IO34,
    IO35,
    IO36,
    IO37,
    VSSA1,
    ANALOG10,
    ANALOG09,
    ANALOG08,
    ANALOG07,
    ANALOG06,
    ANALOG05,
    ANALOG04,
    ANALOG03,
    ANALOG02,
    ANALOG01,
    ANALOG00,
    VDDA1,
    LADATAOUT01,
    LADATAOUT00,
    LADATAOUT02,
    LADATAOUT03,
    LADATAOUT04,
    LADATAOUT05,
    LADATAOUT06,
    LADATAOUT07,
    LADATAOUT08,
    LADATAOUT09,
    LADATAOUT10,
    LADATAOUT11,
    LADATAOUT12,
    LADATAOUT13,
    LADATAOUT14,
    LADATAOUT15,
    LADATA16,
    LADATAOUT17,
    LADATAOUT18,
    LADATAOUT19,
    LADATAOUT20,
    LADATAOUT21,
    LADATAOUT22,
    LADATAOUT23,
    LADATAOUT24,
    LADATAIN00,
    LADATAIN01,
    LADATAIN02,
    LADATAIN03,
    VCCA,
    VNB,
    VPB
);
        inout IO07;
        inout IO08;
        inout IO09;
        inout IO10;
        inout IO11;
        inout IO12;
        inout IO13;
        inout IO25;
        inout IO26;
        inout IO27;
        inout IO28;
        inout IO29;
        inout IO30;
        inout IO31;
        inout IO32;
        inout IO33;
        inout IO34;
        inout IO35;
        inout IO36;
        inout IO37;
        inout VSSA1;
        inout ANALOG10;
        inout ANALOG09;
        inout ANALOG08;
        inout ANALOG07;
        inout ANALOG06;
        inout ANALOG05;
        inout ANALOG04;
        inout ANALOG03;
        inout ANALOG02;
        inout ANALOG01;
        inout ANALOG00;
        inout VDDA1;
        inout LADATAOUT01;
        inout LADATAOUT00;
        inout LADATAOUT02;
        inout LADATAOUT03;
        inout LADATAOUT04;
        inout LADATAOUT05;
        inout LADATAOUT06;
        inout LADATAOUT07;
        inout LADATAOUT08;
        inout LADATAOUT09;
        inout LADATAOUT10;
        inout LADATAOUT11;
        inout LADATAOUT12;
        inout LADATAOUT13;
        inout LADATAOUT14;
        inout LADATAOUT15;
        inout LADATA16;
        inout LADATAOUT17;
        inout LADATAOUT18;
        inout LADATAOUT19;
        inout LADATAOUT20;
        inout LADATAOUT21;
        inout LADATAOUT22;
        inout LADATAOUT23;
        inout LADATAOUT24;
        inout LADATAIN00;
        inout LADATAIN01;
        inout LADATAIN02;
        inout LADATAIN03;
        inout VCCA;
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_TopProtectStructure (
    IO07,
    IO08,
    IO09,
    IO10,
    IO11,
    IO12,
    IO13,
    IO25,
    IO26,
    IO27,
    IO28,
    IO29,
    IO30,
    IO31,
    IO32,
    IO33,
    IO34,
    IO35,
    IO36,
    IO37,
    VSSA1,
    ANALOG10,
    ANALOG09,
    ANALOG08,
    ANALOG07,
    ANALOG06,
    ANALOG05,
    ANALOG04,
    ANALOG03,
    ANALOG02,
    ANALOG01,
    ANALOG00,
    VDDA1,
    LADATAOUT01,
    LADATAOUT00,
    LADATAOUT02,
    LADATAOUT03,
    LADATAOUT04,
    LADATAOUT05,
    LADATAOUT06,
    LADATAOUT07,
    LADATAOUT08,
    LADATAOUT09,
    LADATAOUT10,
    LADATAOUT11,
    LADATAOUT12,
    LADATAOUT13,
    LADATAOUT14,
    LADATAOUT15,
    LADATA16,
    LADATAOUT17,
    LADATAOUT18,
    LADATAOUT19,
    LADATAOUT20,
    LADATAOUT21,
    LADATAOUT22,
    LADATAOUT23,
    LADATAOUT24,
    LADATAIN00,
    LADATAIN01,
    LADATAIN02,
    LADATAIN03,
    VCCA
);
        inout IO07;
        inout IO08;
        inout IO09;
        inout IO10;
        inout IO11;
        inout IO12;
        inout IO13;
        inout IO25;
        inout IO26;
        inout IO27;
        inout IO28;
        inout IO29;
        inout IO30;
        inout IO31;
        inout IO32;
        inout IO33;
        inout IO34;
        inout IO35;
        inout IO36;
        inout IO37;
        inout VSSA1;
        inout ANALOG10;
        inout ANALOG09;
        inout ANALOG08;
        inout ANALOG07;
        inout ANALOG06;
        inout ANALOG05;
        inout ANALOG04;
        inout ANALOG03;
        inout ANALOG02;
        inout ANALOG01;
        inout ANALOG00;
        inout VDDA1;
        inout LADATAOUT01;
        inout LADATAOUT00;
        inout LADATAOUT02;
        inout LADATAOUT03;
        inout LADATAOUT04;
        inout LADATAOUT05;
        inout LADATAOUT06;
        inout LADATAOUT07;
        inout LADATAOUT08;
        inout LADATAOUT09;
        inout LADATAOUT10;
        inout LADATAOUT11;
        inout LADATAOUT12;
        inout LADATAOUT13;
        inout LADATAOUT14;
        inout LADATAOUT15;
        inout LADATA16;
        inout LADATAOUT17;
        inout LADATAOUT18;
        inout LADATAOUT19;
        inout LADATAOUT20;
        inout LADATAOUT21;
        inout LADATAOUT22;
        inout LADATAOUT23;
        inout LADATAOUT24;
        inout LADATAIN00;
        inout LADATAIN01;
        inout LADATAIN02;
        inout LADATAIN03;
        inout VCCA;
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_TOPPROTECTSTRUCTURE


//--------EOF---------

`ifndef SKY130_HILAS_TRANS2MED
`define SKY130_HILAS_TRANS2MED

/**
 * sky130_hilas_Trans2med: None
 *
 * Verilog wrapper for sky130_hilas_Trans2med.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_Trans2med (
    GATE1N,
    GATE2P,
    GATE1P,
    GATE2N,
    SOURCE1P,
    SOURCE2P,
    SOURCE2N,
    SOURCE1N,
    DRAIN1N,
    DRAIN2N,
    DRAIN1P,
    DRAIN2P,
    WELL,
    VGND,
    VNB,
    VPB
);
        inout GATE1N;
        inout GATE2P;
        inout GATE1P;
        inout GATE2N;
        inout SOURCE1P;
        inout SOURCE2P;
        inout SOURCE2N;
        inout SOURCE1N;
        inout DRAIN1N;
        inout DRAIN2N;
        inout DRAIN1P;
        inout DRAIN2P;
        inout WELL;
        inout VGND;
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_Trans2med (
    GATE1N,
    GATE2P,
    GATE1P,
    GATE2N,
    SOURCE1P,
    SOURCE2P,
    SOURCE2N,
    SOURCE1N,
    DRAIN1N,
    DRAIN2N,
    DRAIN1P,
    DRAIN2P,
    WELL
);
        inout GATE1N;
        inout GATE2P;
        inout GATE1P;
        inout GATE2N;
        inout SOURCE1P;
        inout SOURCE2P;
        inout SOURCE2N;
        inout SOURCE1N;
        inout DRAIN1N;
        inout DRAIN2N;
        inout DRAIN1P;
        inout DRAIN2P;
        inout WELL;
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_TRANS2MED


//--------EOF---------

`ifndef SKY130_HILAS_PFETDEVICE01
`define SKY130_HILAS_PFETDEVICE01

/**
 * sky130_hilas_pFETdevice01: pFET transistor used in DAC block
 *
 * Verilog wrapper for sky130_hilas_pFETdevice01.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_pFETdevice01 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_pFETdevice01 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_PFETDEVICE01


//--------EOF---------

`ifndef SKY130_HILAS_DECOUPVINJ00
`define SKY130_HILAS_DECOUPVINJ00

/**
 * sky130_hilas_DecoupVinj00: 
 *
 * Verilog wrapper for sky130_hilas_DecoupVinj00.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_DecoupVinj00 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_DecoupVinj00 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_DECOUPVINJ00


//--------EOF---------

`ifndef SKY130_HILAS_PFETMIRROR
`define SKY130_HILAS_PFETMIRROR

/**
 * sky130_hilas_pFETmirror: pFET current mirror
 *
 * Verilog wrapper for sky130_hilas_pFETmirror.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_pFETmirror (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_pFETmirror (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_PFETMIRROR


//--------EOF---------

`ifndef M12M3
`define M12M3

/**
 * m12m3: 
 *
 * Verilog wrapper for m12m3.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module m12m3 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module m12m3 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // M12M3


//--------EOF---------

`ifndef SKY130_HILAS_DAC6TRANSISTORSTACK01A
`define SKY130_HILAS_DAC6TRANSISTORSTACK01A

/**
 * sky130_hilas_DAC6TransistorStack01a: None
 *
 * Verilog wrapper for sky130_hilas_DAC6TransistorStack01a.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_DAC6TransistorStack01a (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_DAC6TransistorStack01a (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_DAC6TRANSISTORSTACK01A


//--------EOF---------

`ifndef SKY130_HILAS_DECOUP_CAP_00
`define SKY130_HILAS_DECOUP_CAP_00

/**
 * sky130_hilas_decoup_cap_00: decoupling cap (intended as fill)
 *
 * Verilog wrapper for sky130_hilas_decoup_cap_00.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_decoup_cap_00 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_decoup_cap_00 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_DECOUP_CAP_00


//--------EOF---------

`ifndef SKY130_HILAS_M12M2
`define SKY130_HILAS_M12M2

/**
 * sky130_hilas_m12m2: m1 to m2 contact
 *
 * Verilog wrapper for sky130_hilas_m12m2.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_m12m2 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_m12m2 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_M12M2


//--------EOF---------

`ifndef SKY130_HILAS_PFETDEVICE01E
`define SKY130_HILAS_PFETDEVICE01E

/**
 * sky130_hilas_pFETdevice01e: pFET transistor used in DAC block
 *
 * Verilog wrapper for sky130_hilas_pFETdevice01e.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_pFETdevice01e (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_pFETdevice01e (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_PFETDEVICE01E


//--------EOF---------

`ifndef SKY130_HILAS_TGATEDOUBLE01
`define SKY130_HILAS_TGATEDOUBLE01

/**
 * sky130_hilas_TgateDouble01: None
 *
 * Verilog wrapper for sky130_hilas_TgateDouble01.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_TgateDouble01 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_TgateDouble01 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_TGATEDOUBLE01


//--------EOF---------

`ifndef SKY130_HILAS_NOVERLAPCAP01
`define SKY130_HILAS_NOVERLAPCAP01

/**
 * sky130_hilas_nOverlapCap01: overlap capacitor based capacitor (nFET)
 *
 * Verilog wrapper for sky130_hilas_nOverlapCap01.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_nOverlapCap01 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_nOverlapCap01 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_NOVERLAPCAP01


//--------EOF---------

`ifndef SKY130_HILAS_DECOUP_CAP_01
`define SKY130_HILAS_DECOUP_CAP_01

/**
 * sky130_hilas_decoup_cap_01: decoupling cap (intended as fill), variant
 *
 * Verilog wrapper for sky130_hilas_decoup_cap_01.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_decoup_cap_01 (
    VPWR,
    VNB,
    VPB
);
        inout VPWR;
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_decoup_cap_01 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_DECOUP_CAP_01


//--------EOF---------

`ifndef SKY130_HILAS_MCAP2M4
`define SKY130_HILAS_MCAP2M4

/**
 * sky130_hilas_mcap2m4: metal capacitor layer contact to m4
 *
 * Verilog wrapper for sky130_hilas_mcap2m4.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_mcap2m4 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_mcap2m4 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_MCAP2M4


//--------EOF---------

`ifndef SKY130_HILAS_NMIRROR03
`define SKY130_HILAS_NMIRROR03

/**
 * sky130_hilas_nMirror03: None
 *
 * Verilog wrapper for sky130_hilas_nMirror03.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_nMirror03 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_nMirror03 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_NMIRROR03


//--------EOF---------

`ifndef SKY130_HILAS_TUNCAP01
`define SKY130_HILAS_TUNCAP01

/**
 * sky130_hilas_TunCap01: None
 *
 * Verilog wrapper for sky130_hilas_TunCap01.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_TunCap01 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_TunCap01 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_TUNCAP01


//--------EOF---------

`ifndef SKY130_HILAS_NFETLARGEPART1
`define SKY130_HILAS_NFETLARGEPART1

/**
 * sky130_hilas_nFETLargePart1: None
 *
 * Verilog wrapper for sky130_hilas_nFETLargePart1.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_nFETLargePart1 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_nFETLargePart1 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_NFETLARGEPART1


//--------EOF---------

`ifndef SKY130_HILAS_TGATESINGLE01
`define SKY130_HILAS_TGATESINGLE01

/**
 * sky130_hilas_TgateSingle01: None
 *
 * Verilog wrapper for sky130_hilas_TgateSingle01.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_TgateSingle01 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_TgateSingle01 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_TGATESINGLE01


//--------EOF---------

`ifndef SKY130_HILAS_NFET03
`define SKY130_HILAS_NFET03

/**
 * sky130_hilas_nFET03: None
 *
 * Verilog wrapper for sky130_hilas_nFET03.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_nFET03 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_nFET03 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_NFET03


//--------EOF---------

`ifndef SKY130_HILAS_CAPACITORSIZE01
`define SKY130_HILAS_CAPACITORSIZE01

/**
 * sky130_hilas_capacitorSize01: smallest cap
 *
 * Verilog wrapper for sky130_hilas_capacitorSize01.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_capacitorSize01 (
    CAPTERM02,
    CAPTERM01,
    VNB,
    VPB
);
        inout CAPTERM02;
        inout CAPTERM01;
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_capacitorSize01 (
    CAPTERM02,
    CAPTERM01
);
        inout CAPTERM02;
        inout CAPTERM01;
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_CAPACITORSIZE01


//--------EOF---------

`ifndef SKY130_HILAS_DAC6TRANSISTORSTACK01B
`define SKY130_HILAS_DAC6TRANSISTORSTACK01B

/**
 * sky130_hilas_DAC6TransistorStack01b: None
 *
 * Verilog wrapper for sky130_hilas_DAC6TransistorStack01b.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_DAC6TransistorStack01b (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_DAC6TransistorStack01b (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_DAC6TRANSISTORSTACK01B


//--------EOF---------

`ifndef SKY130_HILAS_DECOUPVINJ01
`define SKY130_HILAS_DECOUPVINJ01

/**
 * sky130_hilas_DecoupVinj01: 
 *
 * Verilog wrapper for sky130_hilas_DecoupVinj01.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_DecoupVinj01 (
    VGND,
    VNB,
    VPB
);
        inout VGND;
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_DecoupVinj01 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_DECOUPVINJ01


//--------EOF---------

`ifndef SKY130_HILAS_PFETDEVICE01B
`define SKY130_HILAS_PFETDEVICE01B

/**
 * sky130_hilas_pFETdevice01b: pFET transistor used in DAC block
 *
 * Verilog wrapper for sky130_hilas_pFETdevice01b.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_pFETdevice01b (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_pFETdevice01b (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_PFETDEVICE01B


//--------EOF---------

`ifndef SKY130_HILAS_PTRANSISTORVERT01
`define SKY130_HILAS_PTRANSISTORVERT01

/**
 * sky130_hilas_pTransistorVert01: None
 *
 * Verilog wrapper for sky130_hilas_pTransistorVert01.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_pTransistorVert01 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_pTransistorVert01 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_PTRANSISTORVERT01


//--------EOF---------

`ifndef SKY130_HILAS_TA2SIGNALBIASCELL
`define SKY130_HILAS_TA2SIGNALBIASCELL

/**
 * sky130_hilas_TA2SignalBiasCell: None
 *
 * Verilog wrapper for sky130_hilas_TA2SignalBiasCell.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_TA2SignalBiasCell (
    VOUT_AMP2,
    VOUT_AMP1,
    VIN22,
    VIN21,
    VIN11,
    VIN12,
    VBIAS2,
    VBIAS1,
    VGND,
    VPWR,
    VNB,
    VPB
);
        inout VOUT_AMP2;
        inout VOUT_AMP1;
        inout VIN22;
        inout VIN21;
        inout VIN11;
        inout VIN12;
        inout VBIAS2;
        inout VBIAS1;
        inout VGND;
        inout VPWR;
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_TA2SignalBiasCell (
    VOUT_AMP2,
    VOUT_AMP1,
    VIN22,
    VIN21,
    VIN11,
    VIN12,
    VBIAS2,
    VBIAS1
);
        inout VOUT_AMP2;
        inout VOUT_AMP1;
        inout VIN22;
        inout VIN21;
        inout VIN11;
        inout VIN12;
        inout VBIAS2;
        inout VBIAS1;
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_TA2SIGNALBIASCELL


//--------EOF---------

`ifndef SKY130_HILAS_STEPUPDIGITALPART1
`define SKY130_HILAS_STEPUPDIGITALPART1

/**
 * sky130_hilas_StepUpDigitalPart1: step-up level shifter part
 *
 * Verilog wrapper for sky130_hilas_StepUpDigitalPart1.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_StepUpDigitalPart1 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_StepUpDigitalPart1 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_STEPUPDIGITALPART1


//--------EOF---------

`ifndef SKY130_HILAS_STEPUPDIGITAL
`define SKY130_HILAS_STEPUPDIGITAL

/**
 * sky130_hilas_StepUpDigital: a single level shifter
 *
 * Verilog wrapper for sky130_hilas_StepUpDigital.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_StepUpDigital (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_StepUpDigital (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_STEPUPDIGITAL


//--------EOF---------

`ifndef SKY130_HILAS_TGATE4DOUBLE01
`define SKY130_HILAS_TGATE4DOUBLE01

/**
 * sky130_hilas_Tgate4Double01: 4 double-throw transmission gates
 *
 * Verilog wrapper for sky130_hilas_Tgate4Double01.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_Tgate4Double01 (
    INPUT1_1,
    SELECT1,
    SELECT2,
    INPUT2_2,
    INPUT1_2,
    SELECT3,
    INPUT2_3,
    SELECT4,
    INPUT2_4,
    INPUT1_4,
    OUTPUT4,
    OUTPUT3,
    OUTPUT2,
    OUTPUT1,
    INPUT2_1,
    INPUT1_3,
    VGND,
    VNB,
    VPB
);
        inout INPUT1_1;
        inout SELECT1;
        inout SELECT2;
        inout INPUT2_2;
        inout INPUT1_2;
        inout SELECT3;
        inout INPUT2_3;
        inout SELECT4;
        inout INPUT2_4;
        inout INPUT1_4;
        inout OUTPUT4;
        inout OUTPUT3;
        inout OUTPUT2;
        inout OUTPUT1;
        inout INPUT2_1;
        inout INPUT1_3;
        inout VGND;
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_Tgate4Double01 (
    INPUT1_1,
    SELECT1,
    SELECT2,
    INPUT2_2,
    INPUT1_2,
    SELECT3,
    INPUT2_3,
    SELECT4,
    INPUT2_4,
    INPUT1_4,
    OUTPUT4,
    OUTPUT3,
    OUTPUT2,
    OUTPUT1,
    INPUT2_1,
    INPUT1_3
);
        inout INPUT1_1;
        inout SELECT1;
        inout SELECT2;
        inout INPUT2_2;
        inout INPUT1_2;
        inout SELECT3;
        inout INPUT2_3;
        inout SELECT4;
        inout INPUT2_4;
        inout INPUT1_4;
        inout OUTPUT4;
        inout OUTPUT3;
        inout OUTPUT2;
        inout OUTPUT1;
        inout INPUT2_1;
        inout INPUT1_3;
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_TGATE4DOUBLE01


//--------EOF---------

`ifndef SKY130_HILAS_HORIZTRANSCELL01
`define SKY130_HILAS_HORIZTRANSCELL01

/**
 * sky130_hilas_horizTransCell01: None
 *
 * Verilog wrapper for sky130_hilas_horizTransCell01.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_horizTransCell01 (
    VNB,
    VPB
);
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_horizTransCell01 (
    
);
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_HORIZTRANSCELL01


//--------EOF---------

`ifndef SKY130_HILAS_RESISTOR01
`define SKY130_HILAS_RESISTOR01

/**
 * sky130_hilas_resistor01: 
 *
 * Verilog wrapper for sky130_hilas_resistor01.
 *
 * WARNING: This file is autogenerated, do not modify directly!
 */

`timescale 1ns / 1ps
`default_nettype none


`ifdef USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_resistor01 (
    TERM1,
    TERM2,
    VGND,
    VNB,
    VPB
);
        inout TERM1;
        inout TERM2;
        inout VGND;
        inout VNB;
        inout VPB;
endmodule
`endcelldefine

/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/

`celldefine
module sky130_hilas_resistor01 (
    TERM1,
    TERM2
);
        inout TERM1;
        inout TERM2;
endmodule
`endcelldefine

/*********************************************************/
`endif // USE_POWER_PINS

`default_nettype wire
`endif  // SKY130_HILAS_RESISTOR01


//--------EOF---------