v {xschem version=2.9.9 file_version=1.2 }
G {}
K {type=subcircuit
format="@name @pinlist @symname"
verilog_primitive=true
template="name=x1"
}
V {}
S {}
E {}
L 4 -130 -70 130 -70 {}
L 4 -130 70 130 70 {}
L 4 -130 -70 -130 70 {}
L 4 130 -70 130 70 {}
L 4 -150 -60 -130 -60 {}
L 4 -150 -40 -130 -40 {}
L 4 -150 -20 -130 -20 {}
L 4 -150 0 -130 0 {}
L 4 -150 20 -130 20 {}
L 4 -150 40 -130 40 {}
L 4 -150 60 -130 60 {}
L 7 130 -60 150 -60 {}
L 7 130 -40 150 -40 {}
L 7 130 -20 150 -20 {}
L 7 130 0 150 0 {}
L 7 130 20 150 20 {}
L 7 130 40 150 40 {}
L 7 130 60 150 60 {}
B 5 147.5 -62.5 152.5 -57.5 {name=VINJ dir=inout }
B 5 -152.5 -62.5 -147.5 -57.5 {name=DRAIN1 dir=in }
B 5 -152.5 -42.5 -147.5 -37.5 {name=VBIAS dir=in }
B 5 147.5 -42.5 152.5 -37.5 {name=SOURCE1 dir=inout }
B 5 147.5 -22.5 152.5 -17.5 {name=OUTPUT dir=inout }
B 5 147.5 -2.5 152.5 2.5 {name=VREF dir=inout }
B 5 147.5 17.5 152.5 22.5 {name=VTUN dir=inout }
B 5 -152.5 -22.5 -147.5 -17.5 {name=LARGECAPACITOR dir=in }
B 5 -152.5 -2.5 -147.5 2.5 {name=VTUNOVERLAP01 dir=in }
B 5 -152.5 17.5 -147.5 22.5 {name=GATE4 dir=in }
B 5 -152.5 37.5 -147.5 42.5 {name=GATE2 dir=in }
B 5 -152.5 57.5 -147.5 62.5 {name=GATE3 dir=in }
B 5 147.5 37.5 152.5 42.5 {name=GATE1 dir=inout }
B 5 147.5 57.5 152.5 62.5 {name=VGND dir=inout }
T {FGcharacterization01} -86.5 34 0 0 0.3 0.3 {}
T {@name} 135 -82 0 0 0.2 0.2 {}
T {VINJ} 125 -64 0 1 0.2 0.2 {}
T {DRAIN1} -125 -64 0 0 0.2 0.2 {}
T {VBIAS} -125 -44 0 0 0.2 0.2 {}
T {SOURCE1} 125 -44 0 1 0.2 0.2 {}
T {OUTPUT} 125 -24 0 1 0.2 0.2 {}
T {VREF} 125 -4 0 1 0.2 0.2 {}
T {VTUN} 125 16 0 1 0.2 0.2 {}
T {LARGECAPACITOR} -125 -24 0 0 0.2 0.2 {}
T {VTUNOVERLAP01} -125 -4 0 0 0.2 0.2 {}
T {GATE4} -125 16 0 0 0.2 0.2 {}
T {GATE2} -125 36 0 0 0.2 0.2 {}
T {GATE3} -125 56 0 0 0.2 0.2 {}
T {GATE1} 125 36 0 1 0.2 0.2 {}
T {VGND} 125 56 0 1 0.2 0.2 {}