FULL RUN LOG:
 Executing Step 0 of 9: Extracting GDS Files
Step 0 done without fatal errors.
 Executing Step 1 of 9: Project License Check
{{LICENSE COMPLIANCE PASSED}} Apache-2.0 LICENSE file was found in project root
 SPDX COMPLIANCE Found 60 non-compliant files with the SPDX Standard. Check full log for more information
SPDX COMPLIANCE: NON-COMPLIANT FILES PREVIEW: ['/home/phardytx/Work/mpw2/README.md', '/home/phardytx/Work/mpw2/verilog/rtl/sky130_hilas_sc.v', '/home/phardytx/Work/mpw2/xschem/sky130_hilas_Trans4small.sym', '/home/phardytx/Work/mpw2/xschem/sky130_hilas_TopProtection.sch', '/home/phardytx/Work/mpw2/xschem/sky130_hilas_WTA4Stage01.sch', '/home/phardytx/Work/mpw2/xschem/sky130_hilas_Trans2med.sch', '/home/phardytx/Work/mpw2/xschem/sky130_hilas_DAC5bit01.sch', '/home/phardytx/Work/mpw2/xschem/sky130_hilas_Tgate4Single01.sym', '/home/phardytx/Work/mpw2/xschem/sky130_hilas_pFETLarge.sym', '/home/phardytx/Work/mpw2/xschem/sky130_hilas_LevelShift4InputUp.sch', '/home/phardytx/Work/mpw2/xschem/sky130_hilas_TA2SignalBiasCell.sym', '/home/phardytx/Work/mpw2/xschem/sky130_hilas_drainSelect01.sch', '/home/phardytx/Work/mpw2/xschem/sky130_hilas_TopLevelTestStructure.sch', '/home/phardytx/Work/mpw2/xschem/sky130_hilas_nFETLarge.sym', '/home/phardytx/Work/mpw2/xschem/sky130_hilas_pFETLarge.sch', '/home/phardytx/Work/mpw2/xschem/sky130_hilas_LeftProtection.sch', '/home/phardytx/Work/mpw2/xschem/sky130_hilas_VinjDecode2to4.sym', '/home/phardytx/Work/mpw2/xschem/sky130_hilas_polyresistorGND.sym', '/home/phardytx/Work/mpw2/xschem/sky130_hilas_WTA4Stage01.sym', '/home/phardytx/Work/mpw2/xschem/sky130_hilas_FGBiasWeakGate2x1cell.sym']
 Executing Step 2 of 9: YAML File Check
 YAML file valid!
Step 2 done without fatal errors.
 Detected Project Type is "analog"
 Executing Step 3 of 9: Project Compliance Checks
b'Going into /home/phardytx/Work/mpw2/caravel'
b'Removing manifest'
b'Fetching manifest'
b'Running sha1sum checks'
 Manifest Checks Passed. Caravel Version Matches.
 Makefile Checks Passed.
 Documentation Checks Passed.
 Executing Step 4 of 9: Fuzzy Consistency Checks
instance caravan found
instance user_analog_project_wrapper found
Design is complex and contains: 36 modules
Design is complex and contains: 2 modules
verilog Consistency Checks Passed.
 Basic Hierarchy Checks Passed.
{PROGRESS} Running Pins and Power Checks...
Pins check passed
Internal Power Checks Passed!
Power Checks Passed
 Fuzzy Consistency Checks Passed!
Step 4 done without fatal errors.
 Executing Step 5 of 9: XOR Consistency Checks
 Running XOR Checks...
Total XOR differences = 0
 XOR Checks on User Project GDS Passed!
Step 5 done without fatal errors.
 Executing Step 6 of 9: DRC Violations Checks
 Running Magic DRC Checks...
Violation Message "P-tap minimum area < 0.07011um^2 (psd.10b) "found 12 Times.
Violation Message "MV Butting tap length < 0.7um (diff/tap.16) "found 224 Times.
Violation Message "Poly resistor spacing to poly < 0.48um (poly.9) "found 4 Times.
Violation Message "mcon.spacing < 0.19um (mcon.2) "found 543 Times.
Violation Message "Diffusion contact spacing < 0.17um (licon.2) "found 133 Times.
Violation Message "Metal2 spacing < 0.14um (met2.2) "found 8 Times.
Violation Message "MV Diffusion in N-well to P-tap spacing < 0.76um (diff/tap.20 + diff/tap.17,19) "found 7302 Times.
Violation Message "MV PMOS minimum length < 0.5um (poly.13) "found 94 Times.
Violation Message "All taps must be contacted (licon.16) "found 64 Times.
Violation Message "P-tap overlap of P-tap contact < 0.12um in one direction (licon.7) "found 288 Times.
Violation Message "Butting tap length < 0.29um (diff/tap.4) "found 48 Times.
Violation Message "P-tap spacing to N-well < 0.13um (diff/tap.11) "found 19 Times.
Violation Message "MV Diffusion to MV tap spacing < 0.27um (diff/tap.3) "found 5404 Times.
Violation Message "poly spacing to diffusion tap < 0.055um (poly.5) "found 2 Times.
Violation Message "MV NMOS minimum length < 0.5um (poly.13) "found 17 Times.
Violation Message "P-tap spacing to N-well < 0.005um (diff/tap.11) "found 55 Times.
Violation Message "Transistor width < 0.42um (diff/tap.2) "found 1155 Times.
Violation Message "N-well overlap of varactor poly < 0.15um (varac.5) "found 80 Times.
Violation Message "poly spacing to Diffusion < 0.075um (poly.4) "found 352 Times.
Violation Message "Spacing of HV nwell to LV nwell < 2.0um (nwell.8) "found 58 Times.
Violation Message "No bends in transistors (poly.11) "found 104 Times.
Violation Message "N-tap overlap of N-tap contact < 0.12um in one direction (licon.7) "found 6 Times.
Violation Message "Poly resistor spacing to diffusion < 0.48um (poly.9) "found 101 Times.
Violation Message "poly contact spacing to P-diffusion < 0.235um (licon.9 + psdm.5a) "found 312 Times.
Violation Message "N-well overlap of MV N-tap < 0.33um (diff/tap.19) "found 6549 Times.
Violation Message "MV N-Diffusion to MV P-tap spacing < 0.125um across butted junction (psd.5b) "found 32 Times.
Violation Message "HVNTM spacing < 0.7um (hvntm.2) "found 32 Times.
Violation Message "Spacing of HV nwell to HV nwell < 2.0um (nwell.8) "found 196 Times.
Violation Message "P-tap contact width     < 0.17um (licon.1) "found 48 Times.
 DRC Checks on GDS Failed, Reason: Total # of DRC violations is 23242
TEST FAILED AT STEP 6
 Executing Step 7 of 9: KLayout DRC Violations Check
 Running Klayout DRC Checks...
 Klayout DRC Checks on GDS Failed, Reason: Total # of DRC violations is 43 Please check /home/phardytx/Work/mpw2/checks/user_analog_project_wrapper_klayout_drc.xmlFor more details
TEST FAILED AT STEP 7
 Executing Klayout offgrid check.
 Klayout offgrid Checks on User Project GDS Passed!
Step 8 done without fatal errors.
 Klayout metal minimum clear area density Checks on User Project GDS Passed!
Step 8 done without fatal errors.
 SOME Checks FAILED !!!