v {xschem version=2.9.9 file_version=1.2 }
G {}
K {type=subcircuit
format="@name @pinlist @symname"
verilog_primitive=true
template="name=x1"
}
V {}
S {}
E {}
L 4 -130 -130 130 -130 {}
L 4 -130 130 130 130 {}
L 4 -130 -130 -130 130 {}
L 4 130 -130 130 130 {}
L 4 -150 -120 -130 -120 {}
L 4 -150 -100 -130 -100 {}
L 4 -150 -80 -130 -80 {}
L 4 -150 -60 -130 -60 {}
L 4 -150 -40 -130 -40 {}
L 4 -150 -20 -130 -20 {}
L 4 -150 100 -130 100 {}
L 7 130 -120 150 -120 {}
L 7 130 -100 150 -100 {}
L 7 130 -80 150 -80 {}
L 7 130 -60 150 -60 {}
L 7 130 -40 150 -40 {}
L 7 130 -20 150 -20 {}
L 7 130 0 150 0 {}
L 7 130 20 150 20 {}
L 7 130 40 150 40 {}
L 7 130 60 150 60 {}
L 7 130 80 150 80 {}
L 7 130 100 150 100 {}
L 7 130 120 150 120 {}
B 5 147.5 -122.5 152.5 -117.5 {name=PFET_DRAIN1 dir=inout }
B 5 147.5 -102.5 152.5 -97.5 {name=NFET_DRAIN1 dir=inout }
B 5 -152.5 -122.5 -147.5 -117.5 {name=PFET_GATE1 dir=in }
B 5 147.5 -82.5 152.5 -77.5 {name=WELL dir=inout }
B 5 -152.5 -102.5 -147.5 -97.5 {name=NFET_GATE1 dir=in }
B 5 147.5 -62.5 152.5 -57.5 {name=PFET_SOURCE1 dir=inout }
B 5 147.5 -42.5 152.5 -37.5 {name=NFET_SOURCE1 dir=inout }
B 5 147.5 -22.5 152.5 -17.5 {name=PFET_DRAIN2 dir=inout }
B 5 147.5 -2.5 152.5 2.5 {name=NFET_DRAIN2 dir=inout }
B 5 -152.5 -82.5 -147.5 -77.5 {name=NFET_GATE2 dir=in }
B 5 -152.5 -62.5 -147.5 -57.5 {name=PFET_GATE2 dir=in }
B 5 147.5 17.5 152.5 22.5 {name=PFET_SOURCE2 dir=inout }
B 5 147.5 37.5 152.5 42.5 {name=NFET_SOURCE2 dir=inout }
B 5 147.5 57.5 152.5 62.5 {name=PFET_DRAIN3 dir=inout }
B 5 147.5 77.5 152.5 82.5 {name=NFET_DRAIN3 dir=inout }
B 5 -152.5 -42.5 -147.5 -37.5 {name=PFET_GATE3 dir=in }
B 5 -152.5 -22.5 -147.5 -17.5 {name=NFET_GATE3 dir=in }
B 5 147.5 97.5 152.5 102.5 {name=PFET_SOURCE3 dir=inout }
B 5 147.5 117.5 152.5 122.5 {name=NFET_SOURCE3 dir=inout }
B 5 -152.5 97.5 -147.5 102.5 {name=VGND dir=inout }
T {Trans4small} -47.5 -6 0 0 0.3 0.3 {}
T {@name} 135 -142 0 0 0.2 0.2 {}
T {PFET_DRAIN1} 125 -124 0 1 0.2 0.2 {}
T {NFET_DRAIN1} 125 -104 0 1 0.2 0.2 {}
T {PFET_GATE1} -125 -124 0 0 0.2 0.2 {}
T {WELL} 125 -84 0 1 0.2 0.2 {}
T {NFET_GATE1} -125 -104 0 0 0.2 0.2 {}
T {PFET_SOURCE1} 125 -64 0 1 0.2 0.2 {}
T {NFET_SOURCE1} 125 -44 0 1 0.2 0.2 {}
T {PFET_DRAIN2} 125 -24 0 1 0.2 0.2 {}
T {NFET_DRAIN2} 125 -4 0 1 0.2 0.2 {}
T {NFET_GATE2} -125 -84 0 0 0.2 0.2 {}
T {PFET_GATE2} -125 -64 0 0 0.2 0.2 {}
T {PFET_SOURCE2} 125 16 0 1 0.2 0.2 {}
T {NFET_SOURCE2} 125 36 0 1 0.2 0.2 {}
T {PFET_DRAIN3} 125 56 0 1 0.2 0.2 {}
T {NFET_DRAIN3} 125 76 0 1 0.2 0.2 {}
T {PFET_GATE3} -125 -44 0 0 0.2 0.2 {}
T {NFET_GATE3} -125 -24 0 0 0.2 0.2 {}
T {PFET_SOURCE3} 125 96 0 1 0.2 0.2 {}
T {NFET_SOURCE3} 125 116 0 1 0.2 0.2 {}
T {VGND} -125 96 0 0 0.2 0.2 {}